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AgeCommit message (Collapse)Author
2015-06-02Refactored into core and top.Joachim Strömbergson
2015-05-19Updated TB to use access ports. Added missing invalidate of residue when ↵Joachim Strömbergson
modulus is updated. Minor cleanup.
2015-04-27Updating modexp core to v 0.50. This version contains a working core that ↵Joachim Strömbergson
can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
2015-04-24(1) Adding auto generated testbench for verilog. (2) Update of the test ↵Joachim Strömbergson
generator. (3) Update of the Makefile to run test generator.
2015-04-21Adding more targets for building, linting and simulating submodules.Joachim Strömbergson
2015-04-20Updated Makefile with residue module targets. Updated the license info.Joachim Strömbergson
2015-04-13Adding makefile for linting and for building sim targets.Joachim Strömbergson