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AgeCommit message (Collapse)Author
2015-04-24(1) Adding auto generated testbench for verilog. (2) Update of the test ↵Joachim Strömbergson
generator. (3) Update of the Makefile to run test generator.
2015-04-21Adding more targets for building, linting and simulating submodules.Joachim Strömbergson
2015-04-20Updated Makefile with residue module targets. Updated the license info.Joachim Strömbergson
2015-04-13Adding makefile for linting and for building sim targets.Joachim Strömbergson