| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-06-24 | Fused the s_mem init loop into the adder loop. | Joachim Strömbergson | |
| 2015-06-24 | Small improvement in report of test result. | Joachim Strömbergson | |
| 2015-06-24 | (1) Untangled the word index address generator from the product logic. (2) ↵ | Joachim Strömbergson | |
| Updated the montprod TB to match changed FSM states in montprod. | |||
| 2015-06-22 | Removing stale states in FSM. | Joachim Strömbergson | |
| 2015-06-17 | (1) Collapsed the sm and sa adder states. Thisimoproves performance for ↵ | Joachim Strömbergson | |
| modexp with 3%. (2) Updated montprod testbench to not use the now removed states. (3) Minor code cleanup to make it easier to work with for further improvements. | |||
| 2015-06-16 | Fixed final big testcase to match python model. | Joachim Strömbergson | |
| 2015-06-16 | Collapsing cycles for loop counter. Updating testbench to match removed cycles. | Joachim Strömbergson | |
| 2015-06-16 | Fixed non trivial yet fairly short testcases. | Joachim Strömbergson | |
| 2015-06-15 | Fixed baseline. | Joachim Strömbergson | |
| 2015-06-10 | More cleanup. Adding a lot of compile flags to be able to silence the testbench. | Joachim Strömbergson | |
| 2015-06-10 | Added cycle counter to the montprod testbench to measure the execution time. | Joachim Strömbergson | |
| 2015-06-03 | Adding the encipher/verify test case with 1024 bit RSA key by Rob. | Joachim Strömbergson | |
| 2015-06-02 | Adding sign testcase with 1024 bit operands from real RSA key. | Joachim Strömbergson | |
| 2015-06-02 | Refactored into core and top. | Joachim Strömbergson | |
| 2015-05-24 | Fixed names. | Joachim Strömbergson | |
| 2015-05-24 | Adding two more signing test cases with e=65537 and explicit lengths for ↵ | Joachim Strömbergson | |
| exponent and modulus, message. | |||
| 2015-05-21 | Added internal cycle counter. Added API addresses to extract cycle counter ↵ | Joachim Strömbergson | |
| value. Moved reset of start reg to beginning of FSM. | |||
| 2015-05-20 | (1) Removed unneeded default state. (2) Cleanup of testbench and added a ↵ | Joachim Strömbergson | |
| bigger test case. | |||
| 2015-05-20 | Changed to using modexp length register and removed the common length register. | Joachim Strömbergson | |
| 2015-05-19 | Updated TB to use access ports. Added missing invalidate of residue when ↵ | Joachim Strömbergson | |
| modulus is updated. Minor cleanup. | |||
| 2015-04-27 | Updating modexp core to v 0.50. This version contains a working core that ↵ | Joachim Strömbergson | |
| can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices. | |||
| 2015-04-24 | (1) Adding auto generated testbench for verilog. (2) Update of the test ↵ | Joachim Strömbergson | |
| generator. (3) Update of the Makefile to run test generator. | |||
| 2015-04-20 | Adding testbench for the residue calculator. | Joachim Strömbergson | |
| 2015-04-13 | Adding testbenches for montprod and modexp. The montprod tb has testcases ↵ | Joachim Strömbergson | |
| for up to 1024 bit values. | |||
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index : core/math/modexp | |
| Modular exponentiation core | git repositories |
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