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2015-05-21Added internal cycle counter. Added API addresses to extract cycle counter ↵Joachim Strömbergson
value. Moved reset of start reg to beginning of FSM.
2015-05-20(1) Removed unneeded default state. (2) Cleanup of testbench and added a ↵Joachim Strömbergson
bigger test case.
2015-05-20Changed to using modexp length register and removed the common length register.Joachim Strömbergson
2015-05-19Updated TB to use access ports. Added missing invalidate of residue when ↵Joachim Strömbergson
modulus is updated. Minor cleanup.
2015-04-27Updating modexp core to v 0.50. This version contains a working core that ↵Joachim Strömbergson
can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
2015-04-24(1) Adding auto generated testbench for verilog. (2) Update of the test ↵Joachim Strömbergson
generator. (3) Update of the Makefile to run test generator.
2015-04-20Adding testbench for the residue calculator.Joachim Strömbergson
2015-04-13Adding testbenches for montprod and modexp. The montprod tb has testcases ↵Joachim Strömbergson
for up to 1024 bit values.