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can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
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Update of shl and shr to simplify code. shl and shr could be replaced by functions.
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new shift32 with carry module needed by the residue module.
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for 8192 bit operands. Modexp can build, but lacks proper control and residue generator. Memories has been tested to match block memories in Xilinx and Altera FPGAs.
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