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path: root/src/rtl/modexp.v
AgeCommit message (Collapse)Author
2015-06-02Updated header to emphasis that this is a top level wrapper.Joachim Strömbergson
2015-06-02Refactored into core and top.Joachim Strömbergson
2015-05-24Minor layout fixes.Joachim Strömbergson
2015-05-21Added internal cycle counter. Added API addresses to extract cycle counter ↵Joachim Strömbergson
value. Moved reset of start reg to beginning of FSM.
2015-05-20(1) Removed unneeded default state. (2) Cleanup of testbench and added a ↵Joachim Strömbergson
bigger test case.
2015-05-20Changed to using modexp length register and removed the common length register.Joachim Strömbergson
2015-05-19Updated TB to use access ports. Added missing invalidate of residue when ↵Joachim Strömbergson
modulus is updated. Minor cleanup.
2015-04-27Updated header with info about bit lengths supported.Joachim Strömbergson
2015-04-27Updating modexp core to v 0.50. This version contains a working core that ↵Joachim Strömbergson
can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
2015-04-21Fixed incorrect types.Joachim Strömbergson
2015-04-21Update of modexp to include more of the integration of residue calculator. ↵Joachim Strömbergson
Update of shl and shr to simplify code. shl and shr could be replaced by functions.
2015-04-20(1) Modexp with better API. (2) Adding working residue module. (3) Adding ↵Joachim Strömbergson
new shift32 with carry module needed by the residue module.
2015-04-13Adding initial versions of rtl for modexp. Montgomery multiplication works ↵Joachim Strömbergson
for 8192 bit operands. Modexp can build, but lacks proper control and residue generator. Memories has been tested to match block memories in Xilinx and Altera FPGAs.