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2015-06-03Adding test for for public exponent operation based on Rob 1024 bit key.Joachim Strömbergson
2015-06-02Minor fix for better layout.Joachim Strömbergson
2015-06-02Padded Rob 1024 test with one 32-bit word. This makes the model work for the ↵Joachim Strömbergson
test case.
2015-06-02Cleanup of result checking code to make it easier to see any errors.Joachim Strömbergson
2015-06-02Fixd nits in test case. Added simple line break to clean up.Joachim Strömbergson
2015-06-02Adding 1024 bit test case from Rob to verify that it works in the model.Joachim Strömbergson
2015-05-22Updated the C model with version of modexp that supports explicit, separate ↵Joachim Strömbergson
lengths for exponent and modulus. Also added new test cases, cleaned up code etc.
2015-05-22Removed obsoleted temp parameter.Joachim Strömbergson
2015-05-22Removed file that should not have been in the repo.Joachim Strömbergson
2015-04-27Updating modexp core to v 0.50. This version contains a working core that ↵Joachim Strömbergson
can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
2015-04-24(1) Adding auto generated testbench for verilog. (2) Update of the test ↵Joachim Strömbergson
generator. (3) Update of the Makefile to run test generator.
2015-03-13Adding java rsa functional model.Joachim Strömbergson
2015-03-13Adding c model for the modexp core.Joachim Strömbergson
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Work-in-progress repository with output of altium2kicad conversion of the Cryptech Alpha rev03 board.

The conversion was done using 'convert.sh', with the Altium Designer project files from

https://wiki.cryptech.is/browser/hardware/cad/rev03

and the altium2kicad project from

https://github.com/thesourcerer8/altium2kicad

Current status

NOTE: The latest stable KiCAD version as of this writing is 4.0.7 - it does NOT include necessary support for stitching vias. Install KiCAD nightly build to work with the Cryptech Alpha PCB.

The schematics are successfully converted.

All the copper layers convert reasonably well. The challenges are mostly around filled polygons on the various layers. A python script (fix-pcb.py) modifies parameters to get a fairly close result.

Importing WRL files (3D models) required some hacking of the altium2kicad tool that I haven't been able to work on upstreaming yet.

Another hack that has not been upstreamed is loading more of the source files, IIRC to get all component footprints properly converted.

Issues

Two layers (Altium Gerber files CrypTech.G1 and CrypTech.G2) have fills that I have not been able to reproduce. I targeted not missing any copper, accepting that the KiCAD gerber fills reach more places, so add some copper on those layers.

Drill hole sizes have not been checked. KiCAD seems to add ~0.85 mil more clearance around vias. This needs to be double checked but I'm hoping that we can just tolerate that.