Age | Commit message (Collapse) | Author |
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modexp with 3%. (2) Updated montprod testbench to not use the now removed states. (3) Minor code cleanup to make it easier to work with for further improvements.
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counter. (3) Reordered processes to main datapath first.
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test case.
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exponent and modulus, message.
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lengths for exponent and modulus. Also added new test cases, cleaned up code etc.
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value. Moved reset of start reg to beginning of FSM.
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bigger test case.
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modulus is updated. Minor cleanup.
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can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.
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generator. (3) Update of the Makefile to run test generator.
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Update of shl and shr to simplify code. shl and shr could be replaced by functions.
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new shift32 with carry module needed by the residue module.
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