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-rw-r--r--src/rtl/adder32.v42
-rw-r--r--src/rtl/montprod.v64
-rw-r--r--src/rtl/residue.v61
-rw-r--r--src/rtl/shl32.v31
-rw-r--r--src/rtl/shr32.v25
5 files changed, 119 insertions, 104 deletions
diff --git a/src/rtl/adder32.v b/src/rtl/adder32.v
index d9cac45..fa8ed8c 100644
--- a/src/rtl/adder32.v
+++ b/src/rtl/adder32.v
@@ -1,11 +1,12 @@
//======================================================================
//
-// adder32.v
-// ---------
-// 32bit adder with carry in / carry out
+// adder.v
+// -------
+// Adder with separate carry in and carry out. Used in the montprod
+// amd residue modules of the modexp core.
//
//
-// Author: Peter Magnusson
+// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -36,19 +37,28 @@
//
//======================================================================
+module adder #(parameter OPW = 32)
+ (
+ input [(OPW - 1) : 0] a,
+ input [(OPW - 1) : 0] b,
+ input carry_in,
-module adder32(
- input [31 : 0] a,
- input [31 : 0] b,
- input carry_in,
- output wire [31 : 0] sum,
- output wire carry_out);
+ output wire [(OPW - 1) : 0] sum,
+ output wire carry_out
+ );
- reg [32 : 0] adder_result;
+ reg [(OPW) : 0] adder_result;
- assign sum = adder_result[31:0];
- assign carry_out = adder_result[32];
+ assign sum = adder_result[(OPW - 1) : 0];
+ assign carry_out = adder_result[(OPW)];
- always @(a, b, carry_in)
- adder_result = {1'b0, a} + {1'b0, b} + {32'b0, carry_in};
-endmodule
+ always @*
+ begin
+ adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in};
+ end
+
+endmodule // adder
+
+//======================================================================
+// EOF adder.v
+//======================================================================
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 465fa38..ffee748 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -186,38 +186,38 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
- blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
- .clk(clk),
- .read_addr(s_mem_addr),
- .read_data(s_mem_read_data),
- .wr(s_mem_we_reg),
- .write_addr(s_mem_wr_addr_reg),
- .write_data(s_mem_new)
- );
-
- adder32 s_adder_sm(
- .a(muxed_s_mem_read_data),
- .b(opm_data),
- .carry_in(add_carry_in_sm_reg),
- .sum(add_result_sm),
- .carry_out(add_carry_out_sm)
- );
-
-
- adder32 s_adder_sa(
- .a(sa_adder_data_in),
- .b(opa_data),
- .carry_in(add_carry_in_sa_reg),
- .sum(add_result_sa),
- .carry_out(add_carry_out_sa)
- );
-
- shr32 shifter(
- .a(s_mem_read_data),
- .carry_in(shr_carry_in_reg),
- .adiv2(shr_data_out),
- .carry_out(shr_carry_out)
- );
+ blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
+ .clk(clk),
+ .read_addr(s_mem_addr),
+ .read_data(s_mem_read_data),
+ .wr(s_mem_we_reg),
+ .write_addr(s_mem_wr_addr_reg),
+ .write_data(s_mem_new)
+ );
+
+ adder #(.OPW(OPW)) s_adder_sm(
+ .a(muxed_s_mem_read_data),
+ .b(opm_data),
+ .carry_in(add_carry_in_sm_reg),
+ .sum(add_result_sm),
+ .carry_out(add_carry_out_sm)
+ );
+
+
+ adder #(.OPW(OPW)) s_adder_sa(
+ .a(sa_adder_data_in),
+ .b(opa_data),
+ .carry_in(add_carry_in_sa_reg),
+ .sum(add_result_sa),
+ .carry_out(add_carry_out_sa)
+ );
+
+ shr #(.OPW(OPW)) shifter(
+ .a(s_mem_read_data),
+ .carry_in(shr_carry_in_reg),
+ .adiv2(shr_data_out),
+ .carry_out(shr_carry_out)
+ );
//----------------------------------------------------------------
diff --git a/src/rtl/residue.v b/src/rtl/residue.v
index 3fa1666..ccfaeda 100644
--- a/src/rtl/residue.v
+++ b/src/rtl/residue.v
@@ -45,26 +45,26 @@
//
//======================================================================
-module residue(
- input wire clk,
- input wire reset_n,
+module residue #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
+ input wire reset_n,
- input wire calculate,
- output wire ready,
+ input wire calculate,
+ output wire ready,
- input wire [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
- input wire [07 : 0] length,
+ input wire [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
+ input wire [07 : 0] length,
- output wire [07 : 0] opa_rd_addr,
- input wire [31 : 0] opa_rd_data,
- output wire [07 : 0] opa_wr_addr,
- output wire [31 : 0] opa_wr_data,
- output wire opa_wr_we,
+ output wire [07 : 0] opa_rd_addr,
+ input wire [31 : 0] opa_rd_data,
+ output wire [07 : 0] opa_wr_addr,
+ output wire [31 : 0] opa_wr_data,
+ output wire opa_wr_we,
- output wire [07 : 0] opm_addr,
- input wire [31 : 0] opm_data
-
-);
+ output wire [07 : 0] opm_addr,
+ input wire [31 : 0] opm_data
+ );
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@@ -143,21 +143,20 @@ assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
- adder32 subcmp(
- .a(opa_rd_data),
- .b( ~ opm_data),
- .carry_in(sub_carry_in_reg),
- .sum(sub_data),
- .carry_out(sub_carry_out)
- );
-
- shl32 shl(
- .a(opa_rd_data),
- .carry_in(shl_carry_in_reg),
- .amul2(shl_data),
- .carry_out(shl_carry_out)
- );
-
+ adder #(.OPW(OPW)) add_inst(
+ .a(opa_rd_data),
+ .b( ~ opm_data),
+ .carry_in(sub_carry_in_reg),
+ .sum(sub_data),
+ .carry_out(sub_carry_out)
+ );
+
+ shl #(.OPW(OPW)) shl_inst(
+ .a(opa_rd_data),
+ .carry_in(shl_carry_in_reg),
+ .amul2(shl_data),
+ .carry_out(shl_carry_out)
+ );
//----------------------------------------------------------------
diff --git a/src/rtl/shl32.v b/src/rtl/shl32.v
index 42521fd..bed83e8 100644
--- a/src/rtl/shl32.v
+++ b/src/rtl/shl32.v
@@ -1,11 +1,12 @@
//======================================================================
//
-// shl32.v
-// -------
-// 32bit left shift with carry in / carry out
+// shl.v
+// -----
+// One bit left shift of words with carry in and carry out. Used in
+// the residue module of the modexp core.
//
//
-// Author: Peter Magnusson
+// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -36,18 +37,20 @@
//
//======================================================================
-module shl32(
- input wire [31 : 0] a,
- input wire carry_in,
- output wire [31 : 0] amul2,
- output wire carry_out
- );
+module shl #(parameter OPW = 32)
+ (
+ input wire [(OPW - 1) : 0] a,
+ input wire carry_in,
- assign amul2 = {a[30 : 0], carry_in};
- assign carry_out = a[31];
+ output wire [(OPW - 1) : 0] amul2,
+ output wire carry_out
+ );
-endmodule // shl32
+ assign amul2 = {a[(OPW - 2) : 0], carry_in};
+ assign carry_out = a[(OPW - 1)];
+
+endmodule // shl
//======================================================================
-// EOF shl32.v
+// EOF shl.v
//======================================================================
diff --git a/src/rtl/shr32.v b/src/rtl/shr32.v
index 66b15c3..40ef111 100644
--- a/src/rtl/shr32.v
+++ b/src/rtl/shr32.v
@@ -2,10 +2,11 @@
//
// shr32.v
// -------
-// 32bit right shift with carry in / carry out.
+// One bit right shift with carry in and carry out.
+// Used in the montprod module of the modexp core.
//
//
-// Author: Peter Magnusson
+// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -36,18 +37,20 @@
//
//======================================================================
-module shr32(
- input wire [31 : 0] a,
- input wire carry_in,
- output wire [31 : 0] adiv2,
- output wire carry_out
- );
+module shr #(parameter OPW = 32)
+ (
+ input wire [(OPW - 1) : 0] a,
+ input wire carry_in,
- assign adiv2 = {carry_in, a[31 : 1]};
+ output wire [(OPW - 1) : 0] adiv2,
+ output wire carry_out
+ );
+
+ assign adiv2 = {carry_in, a[(OPW - 1) : 1]};
assign carry_out = a[0];
-endmodule // shr32
+endmodule // shr
//======================================================================
-// EOF shr32.v
+// EOF shr.v
//======================================================================
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 18:19:47 +0000