diff options
Diffstat (limited to 'src/tb')
| -rw-r--r-- | src/tb/tb_modexp.v | 249 |
1 files changed, 174 insertions, 75 deletions
diff --git a/src/tb/tb_modexp.v b/src/tb/tb_modexp.v index a7159b7..0bb81e8 100644 --- a/src/tb/tb_modexp.v +++ b/src/tb/tb_modexp.v @@ -6,33 +6,33 @@ // // // Author: Joachim Strombergson, Peter Magnusson -// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// Copyright (c) 2015, Assured AB +// All rights reserved. // -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: // -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. // -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -50,48 +50,53 @@ module tb_modexp(); //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter DEBUG = 0; - parameter DEBUG_EI = 1; + // Debug output control. + parameter DEBUG = 0; + parameter DEBUG_EI = 0; + parameter DISPLAY_TEST_CYCLES = 1; + + // Clock defines. localparam CLK_HALF_PERIOD = 1; localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD; + // The DUT address map. - localparam GENERAL_PREFIX = 4'h0; - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; + localparam GENERAL_PREFIX = 4'h0; + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; - localparam ADDR_CTRL = 8'h08; - localparam CTRL_START_BIT = 0; + localparam ADDR_CTRL = 8'h08; + localparam CTRL_START_BIT = 0; - localparam ADDR_STATUS = 8'h09; - localparam STATUS_READY_BIT = 0; + localparam ADDR_STATUS = 8'h09; + localparam STATUS_READY_BIT = 0; - localparam ADDR_MODULUS_LENGTH = 8'h20; - localparam ADDR_MESSAGE_LENGTH = 8'h21; - localparam ADDR_EXPONENT_LENGTH = 8'h22; + localparam ADDR_MODULUS_LENGTH = 8'h20; + localparam ADDR_EXPONENT_LENGTH = 8'h21; + localparam ADDR_LENGTH = 8'h22; - localparam MODULUS_PREFIX = 4'h1; - localparam ADDR_MODULUS_START = 8'h00; - localparam ADDR_MODULUS_END = 8'hff; + localparam ADDR_MODULUS_PTR_RST = 8'h30; + localparam ADDR_MODULUS_DATA = 8'h31; - localparam EXPONENT_PREFIX = 4'h2; - localparam ADDR_EXPONENT_START = 8'h00; - localparam ADDR_EXPONENT_END = 8'hff; + localparam ADDR_EXPONENT_PTR_RST = 8'h40; + localparam ADDR_EXPONENT_DATA = 8'h41; - localparam MESSAGE_PREFIX = 4'h3; - localparam MESSAGE_START = 8'h00; - localparam MESSAGE_END = 8'hff; + localparam ADDR_MESSAGE_PTR_RST = 8'h50; + localparam ADDR_MESSAGE_DATA = 8'h51; - localparam RESULT_PREFIX = 4'h4; - localparam RESULT_START = 8'h00; - localparam RESULT_END = 8'hff; + localparam ADDR_RESULT_PTR_RST = 8'h60; + localparam ADDR_RESULT_DATA = 8'h61; //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- + reg [31 : 0] test_cycle_ctr; + reg test_cycle_ctr_rst; + reg test_cycle_ctr_inc; + reg [31 : 0] cycle_ctr; reg [31 : 0] error_ctr; reg [31 : 0] tc_ctr; @@ -153,12 +158,62 @@ module tb_modexp(); end end + + //---------------------------------------------------------------- + // test_cycle_counter + // + // Used to measure the number of cycles it takes to perform + // a given test case. + //---------------------------------------------------------------- + always @ (posedge tb_clk) + begin + if (test_cycle_ctr_rst) + test_cycle_ctr = 64'h0000000000000000; + + if (test_cycle_ctr_inc) + test_cycle_ctr = test_cycle_ctr + 1; + end + + + //---------------------------------------------------------------- + // start_test_cycle_ctr + // + // Reset and start the test cycle counter. + //---------------------------------------------------------------- + task start_test_cycle_ctr(); + begin + test_cycle_ctr_rst = 1; + #(CLK_PERIOD); + test_cycle_ctr_rst = 0; + + test_cycle_ctr_inc = 1; + end + endtask // start_test_cycle_ctr() + + + //---------------------------------------------------------------- + // stop_test_cycle_ctr() + // + // Stop the test cycle counter and optionally display the + // result. + //---------------------------------------------------------------- + task stop_test_cycle_ctr(); + begin + test_cycle_ctr_inc = 0; + #(CLK_PERIOD); + + if (DISPLAY_TEST_CYCLES) + $display("*** Number of cycles performed during test: 0x%016x", test_cycle_ctr); + end + endtask // stop_test_cycle_ctr() + + //---------------------------------------------------------------- // ei_monitor() // // Displays ei_new, the most important variable for determining - // what modexp will do (i.e. should Z=MONTPROD( Z, P, M) be - // performed + // what modexp will do (i.e. should Z=MONTPROD( Z, P, M) be + // performed //---------------------------------------------------------------- always @* begin : ei_monitor @@ -307,7 +362,7 @@ module tb_modexp(); tb_write_data = word; tb_cs = 1; tb_we = 1; - #(2 * CLK_PERIOD); + #(CLK_PERIOD); tb_cs = 0; tb_we = 0; end @@ -484,22 +539,31 @@ module tb_modexp(); $display("TC1: Trying to calculate 3**7 mod 11 = 9"); // Write 3 to message memory. - write_word({MESSAGE_PREFIX, 8'h00}, 32'h00000003); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000003); + write_word({GENERAL_PREFIX, ADDR_LENGTH}, 32'h00000001); // Write 7 to exponent memory and set length to one word. - write_word({EXPONENT_PREFIX, 8'h00}, 32'h00000007); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000007); write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); // Write 11 to modulus memory and set length to one word. - write_word({MODULUS_PREFIX, 8'h00}, 32'h0000000b); + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0000000b); write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001); + start_test_cycle_ctr(); + // Start processing and wait for ready. write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); wait_ready(); + stop_test_cycle_ctr(); + // Read out result word and check result. - read_word({RESULT_PREFIX, 8'h00}); + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; if (read_data == 32'h00000009) @@ -534,23 +598,32 @@ module tb_modexp(); tc_ctr = tc_ctr + 1; $display("TC2: Trying to calculate 251**251 mod 257 = 183"); - // Write 13 to (m)esaage memory. - write_word({MESSAGE_PREFIX, 8'h00}, 32'h000000fb); + // Write 13 to message memory. + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h000000fb); + write_word({GENERAL_PREFIX, ADDR_LENGTH}, 32'h00000001); // Write 11 to exponent memory and set length to one word. - write_word({EXPONENT_PREFIX, 8'h00}, 32'h000000fb); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h000000fb); write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); // Write 7 to modulus memory and set length to one word. - write_word({MODULUS_PREFIX, 8'h00}, 32'h00000101); + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000101); write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001); + start_test_cycle_ctr(); + // Start processing and wait for ready. write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); wait_ready(); + stop_test_cycle_ctr(); + // Read out result word and check result. - read_word({RESULT_PREFIX, 8'h00}); + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; if (read_data == 32'h000000b7) @@ -561,7 +634,7 @@ module tb_modexp(); else begin $display("*** ERROR: TC2 NOT successful."); - $display("Expected: 0x06, got 0x%08x", read_data); + $display("Expected: 0x000000b7, got 0x%08x", read_data); error_ctr = error_ctr + 1; end end @@ -584,22 +657,31 @@ module tb_modexp(); tc_ctr = tc_ctr + 1; $display("TC3: Trying to calculate 0x81 ** 0x41 mod 0x87 = 0x36"); - write_word({MESSAGE_PREFIX, 8'h00}, 32'h00000081); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000081); + write_word({GENERAL_PREFIX, ADDR_LENGTH}, 32'h00000001); // Write 11 to exponent memory and set length to one word. - write_word({EXPONENT_PREFIX, 8'h00}, 32'h00000041); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000041); write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); // Write 7 to modulus memory and set length to one word. - write_word({MODULUS_PREFIX, 8'h00}, 32'h00000087); + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000087); write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001); + start_test_cycle_ctr(); + // Start processing and wait for ready. write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); wait_ready(); + stop_test_cycle_ctr(); + // Read out result word and check result. - read_word({RESULT_PREFIX, 8'h00}); + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; if (read_data == 32'h00000036) @@ -616,6 +698,9 @@ module tb_modexp(); end endtask // tc3 + + //---------------------------------------------------------------- + //---------------------------------------------------------------- function assertEquals( input [31:0] expected, input [31:0] actual @@ -635,6 +720,9 @@ module tb_modexp(); integer success; + + //---------------------------------------------------------------- + //---------------------------------------------------------------- task autogenerated_BASIC_M4962768465676381896(); reg [31 : 0] read_data; begin @@ -642,25 +730,36 @@ module tb_modexp(); tc_ctr = tc_ctr + 1; $display("autogenerated_BASIC_M4962768465676381896: 00000001946473e1 ** h000000010e85e74f mod 0000000170754797 "); - write_word({MESSAGE_PREFIX, 8'h00}, 32'h00000001); //TEMPLATE_MESSAGE_VALES - write_word({MESSAGE_PREFIX, 8'h01}, 32'h946473e1); //TEMPLATE_MESSAGE_VALES - write_word({EXPONENT_PREFIX, 8'h00}, 32'h00000001); //TEMPLATE_EXPONENT_VALES - write_word({EXPONENT_PREFIX, 8'h01}, 32'h0e85e74f); //TEMPLATE_EXPONENT_VALES - write_word({MODULUS_PREFIX, 8'h00}, 32'h00000001); //TEMPLATE_MODULUS_VALUES - write_word({MODULUS_PREFIX, 8'h01}, 32'h70754797); //TEMPLATE_MODULUS_VALUES + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000001); //TEMPLATE_MESSAGE_VALUES + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h946473e1); //TEMPLATE_MESSAGE_VALUES + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000001); //TEMPLATE_EXPONENT_VALUES + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h0e85e74f); //TEMPLATE_EXPONENT_VALUES + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000001); //TEMPLATE_MODULUS_VALUES + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h70754797); //TEMPLATE_MODULUS_VALUES write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000002); //TEMPLATE_MESSAGE_LENGTH write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000002); //TEMPLATE_MODULUS_LENGTH + write_word({GENERAL_PREFIX, ADDR_LENGTH}, 32'h00000002); //TEMPLATE_LENGTH + + start_test_cycle_ctr(); // Start processing and wait for ready. write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); wait_ready(); - read_word({RESULT_PREFIX, 8'h00}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({RESULT_PREFIX, 8'h01}); read_data = tb_read_data; success = success & assertEquals(32'h7761ed4f, read_data); //TEMPLATE_EXPECTED_VALUES - + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); //TEMPLATE_EXPECTED_VALUES + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7761ed4f, read_data); //TEMPLATE_EXPECTED_VALUES + if (success !== 1) - begin + begin $display("*** ERROR: autogenerated_BASIC_M4962768465676381896 was NOT successful."); error_ctr = error_ctr + 1; end |