diff options
Diffstat (limited to 'src/tb')
| -rw-r--r-- | src/tb/tb_modexp.v | 1028 | ||||
| -rw-r--r-- | src/tb/tb_modexp_autogenerated.v | 4 | ||||
| -rw-r--r-- | src/tb/tb_montprod.v | 757 |
3 files changed, 1394 insertions, 395 deletions
diff --git a/src/tb/tb_modexp.v b/src/tb/tb_modexp.v index c2ab7fb..637d5a7 100644 --- a/src/tb/tb_modexp.v +++ b/src/tb/tb_modexp.v @@ -6,33 +6,33 @@ // // // Author: Joachim Strombergson, Peter Magnusson -// Copyright (c) 2015, Assured AB -// All rights reserved. +// Copyright (c) 2015, NORDUnet A/S All rights reserved. // -// Redistribution and use in source and binary forms, with or -// without modification, are permitted provided that the following -// conditions are met: +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. // -// 1. Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. // -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. // -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //====================================================================== @@ -256,8 +256,8 @@ module tb_modexp(); dut.core_inst.ready_reg, dut.start_reg, dut.start_new); $display("residue_valid = 0x%01x", dut.core_inst.residue_valid_reg); $display("loop_counter_reg = 0x%08x", dut.core_inst.loop_counter_reg); - $display("exponent_length_reg = 0x%02x, modulus_length_reg = 0x%02x length_m1 = 0x%02x", - dut.exponent_length_reg, dut.modulus_length_reg, dut.core_inst.length_m1); + $display("exponent_length_reg = 0x%02x exponent_length_m1 = 0x%02x modulus_length_reg = 0x%02x modulus_length_m1 = 0x%02x", + dut.exponent_length_reg, dut.core_inst.exponent_length_m1, dut.modulus_length_reg, dut.core_inst.modulus_length_m1); $display("ctrl_reg = 0x%04x", dut.core_inst.modexp_ctrl_reg); $display(""); end @@ -786,26 +786,28 @@ module tb_modexp(); tc_ctr = tc_ctr + 1; $display("autogenerated_BASIC_128bit"); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h29462882); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h12caa2d5); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb80e1c66); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1006807f); - write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3285c343); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2acbcb0f); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h4d023228); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2ecc73db); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h29462882); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h12caa2d5); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb80e1c66); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1006807f); + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h267d2f2e); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h51c216a7); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hda752ead); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h48d22d89); write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000004); - write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000004); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005); start_test_cycle_ctr(); @@ -816,10 +818,11 @@ module tb_modexp(); stop_test_cycle_ctr(); write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data); //TEMPLATE_EXPECTED_VALUES + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data); if (success !== 1) begin @@ -833,6 +836,57 @@ module tb_modexp(); //---------------------------------------------------------------- + // e64bit_64bit_modulus() + //---------------------------------------------------------------- + task e64bit_64bit_modulus(); + reg [31 : 0] read_data; + begin + success = 32'h1; + tc_ctr = tc_ctr + 1; + $display("Test with 64 bit exponent and 64 bit modulus."); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h12345678); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h97543211); + + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfeababab); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hdeadbeef); + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffee); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbeefbeef); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000002); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003); + + start_test_cycle_ctr(); + + // Start processing and wait for ready. + write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); + wait_ready(); + + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'he52c5b9f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h85de87eb, read_data); + + if (success !== 1) + begin + $display("*** ERROR: 64 bit exponent and 64 bit_modulus was NOT successful."); + error_ctr = error_ctr + 1; + end + else + $display("*** 64 bit exponent and 64 bit modulus success."); + end + endtask // e64bit_64bit_modulus + + + //---------------------------------------------------------------- // e65537_64bit_modulus() //---------------------------------------------------------------- task e65537_64bit_modulus(); @@ -846,15 +900,17 @@ module tb_modexp(); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b); write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3); write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b); write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); - write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000002); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003); start_test_cycle_ctr(); @@ -865,8 +921,9 @@ module tb_modexp(); stop_test_cycle_ctr(); write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h419a024f, read_data); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdddf178e, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data); if (success !== 1) begin @@ -880,6 +937,56 @@ module tb_modexp(); //---------------------------------------------------------------- + // e65537_64bit_modulus_elength() + //---------------------------------------------------------------- + task e65537_64bit_modulus_elength(); + reg [31 : 0] read_data; + begin + success = 32'h1; + tc_ctr = tc_ctr + 1; + $display("Test with e = 65537 and 64 bit modulus, explicit exponent length."); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b); + + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003); + + start_test_cycle_ctr(); + + // Start processing and wait for ready. + write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); + wait_ready(); + + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data); + + if (success !== 1) + begin + $display("*** ERROR: e65537_64bit_modulus with explicit elength was NOT successful."); + error_ctr = error_ctr + 1; + end + else + $display("*** e65537_64bit_modulus success."); + end + endtask // e65537_64bit_modulus_elength + + + //---------------------------------------------------------------- // e65537_128bit_modulus() //---------------------------------------------------------------- task e65537_128bit_modulus(); @@ -893,19 +1000,21 @@ module tb_modexp(); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf5e8eee0); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc06b048a); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h964b2105); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h2c36ad6b); write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h956e61b3); write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h27997bc4); write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h94e7e5c9); write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb53585cf); write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); - write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000004); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005); start_test_cycle_ctr(); @@ -916,10 +1025,11 @@ module tb_modexp(); stop_test_cycle_ctr(); write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h1e97bff8, read_data); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h60029e6e, read_data); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hedaef85e, read_data); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hfb0c6562, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h9c6d322c, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h25ab8bd3, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4aa80100, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf0f3a02c, read_data); if (success !== 1) begin @@ -947,17 +1057,8 @@ module tb_modexp(); write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf169d36e); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbe2ce61d); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hc2e87809); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4fed15c3); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h7c70eac5); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha123e643); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h299b36d2); - write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h788e583b); - write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf169d36e); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbe2ce61d); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc2e87809); @@ -967,8 +1068,19 @@ module tb_modexp(); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h299b36d2); write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h788e583b); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf169d36e); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbe2ce61d); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hc2e87809); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4fed15c3); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h7c70eac5); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha123e643); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h299b36d2); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h788e583a); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); - write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000008); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000009); start_test_cycle_ctr(); @@ -979,10 +1091,15 @@ module tb_modexp(); stop_test_cycle_ctr(); write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data); //TEMPLATE_EXPECTED_VALUES - read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data); //TEMPLATE_EXPECTED_VALUES + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf169d36e, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hbe2ce61d, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hc2e87809, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4fed15c3, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7c70eac5, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha123e643, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h299b36d2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h788e583a, read_data); if (success !== 1) begin @@ -996,6 +1113,790 @@ module tb_modexp(); //---------------------------------------------------------------- + // e65537_1024bit_modulus() + // + // Task that tests modexp with small exponent and + // 2048 bit modulus. + //---------------------------------------------------------------- + task e65537_1024bit_modulus(); + reg [31 : 0] read_data; + begin + success = 32'h1; + tc_ctr = tc_ctr + 1; + $display("Test with e = 65537 and 1024 bit modulus."); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + + + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021); + + start_test_cycle_ctr(); + + // Start processing and wait for ready. + write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); + wait_ready(); + + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data); + + if (success !== 1) + begin + $display("*** ERROR: e65537_1024bit_modulus was NOT successful."); + error_ctr = error_ctr + 1; + end + else + $display("*** e65537_1024bit_modulus success."); + end + endtask // e65537_1024bit_modulus + + + //---------------------------------------------------------------- + // e65537_1536bit_modulus() + // + // Task that tests modexp with small exponent and + // 1536 bit modulus. + //---------------------------------------------------------------- + task e65537_1536bit_modulus(); + reg [31 : 0] read_data; + begin + success = 32'h1; + tc_ctr = tc_ctr + 1; + $display("Test with e = 65537 and 1536 bit modulus."); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + + + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000031); + + start_test_cycle_ctr(); + + // Start processing and wait for ready. + write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); + wait_ready(); + + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data); + + if (success !== 1) + begin + $display("*** ERROR: e65537_1536bit_modulus was NOT successful."); + error_ctr = error_ctr + 1; + end + else + $display("*** e65537_1536bit_modulus success."); + end + endtask // e65537_1536bit_modulus + + + + //---------------------------------------------------------------- + // e65537_1664bit_modulus() + // + // Task that tests modexp with small exponent and + // 1664 bit modulus. + //---------------------------------------------------------------- + task e65537_1664bit_modulus(); + reg [31 : 0] read_data; + begin + success = 32'h1; + tc_ctr = tc_ctr + 1; + $display("Test with e = 65537 and 1664 bit modulus."); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + + + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000035); + + start_test_cycle_ctr(); + + // Start processing and wait for ready. + write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); + wait_ready(); + + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data); + + if (success !== 1) + begin + $display("*** ERROR: e65537_1664bit_modulus was NOT successful."); + error_ctr = error_ctr + 1; + end + else + $display("*** e65537_1664it_modulus success."); + end + endtask // e65537_1664bit_modulus + + + //---------------------------------------------------------------- + // e65537_2048bit_modulus() + // + // Task that tests modexp with small exponent and + // 2048 bit modulus. + //---------------------------------------------------------------- + task e65537_2048bit_modulus(); + reg [31 : 0] read_data; + begin + success = 32'h1; + tc_ctr = tc_ctr + 1; + $display("Test with e = 65537 and 2048 bit modulus."); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001); + + write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef); + + + write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc); + write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff); + + write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001); + write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000041); + + start_test_cycle_ctr(); + + // Start processing and wait for ready. + write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001); + wait_ready(); + + stop_test_cycle_ctr(); + + write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data); + + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data); + read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data); + + if (success !== 1) + begin + $display("*** ERROR: e65537_2048bit_modulus was NOT successful."); + error_ctr = error_ctr + 1; + end + else + $display("*** e65537_2048bit_modulus success."); + end + endtask // e65537_2048bit_modulus + + + //---------------------------------------------------------------- // rob_dec_1024() // // Task that tests modexp with 1024 bit decipher/sign with @@ -1373,12 +2274,17 @@ module tb_modexp(); // tc3(); // autogenerated_BASIC_33bit(); // autogenerated_BASIC_128bit(); +// e64bit_64bit_modulus(); // e65537_64bit_modulus(); +// e65537_64bit_modulus_elength(); // e65537_128bit_modulus(); // e65537_256bit_modulus(); - +// e65537_1024bit_modulus(); +// e65537_1536bit_modulus(); +// e65537_1664bit_modulus(); + e65537_2048bit_modulus(); // rob_dec_1024(); - rob_enc_1024(); +// rob_enc_1024(); display_test_results(); diff --git a/src/tb/tb_modexp_autogenerated.v b/src/tb/tb_modexp_autogenerated.v index 1eb80d5..0bb9432 100644 --- a/src/tb/tb_modexp_autogenerated.v +++ b/src/tb/tb_modexp_autogenerated.v @@ -174,8 +174,8 @@ module tb_modexp_autogenerated(); dut.core_inst.ready_reg, dut.start_reg, dut.start_new); $display("residue_valid = 0x%01x", dut.core_inst.residue_valid_reg); $display("loop_counter_reg = 0x%08x", dut.core_inst.loop_counter_reg); - $display("exponent_length_reg = 0x%02x, modulus_length_reg = 0x%02x length_m1 = 0x%02x", - dut.exponent_length_reg, dut.modulus_length_reg, dut.core_inst.length_m1); + $display("exponent_length_reg = 0x%02x, modulus_length_reg = 0x%02x modulus_length_m1 = 0x%02x", + dut.exponent_length_reg, dut.modulus_length_reg, dut.core_inst.modulus_length_m1); $display("ctrl_reg = 0x%04x", dut.core_inst.modexp_ctrl_reg); $display(""); end diff --git a/src/tb/tb_montprod.v b/src/tb/tb_montprod.v index 601e7f8..cd27949 100644 --- a/src/tb/tb_montprod.v +++ b/src/tb/tb_montprod.v @@ -41,373 +41,466 @@ //------------------------------------------------------------------ `timescale 1ns/100ps -//------------------------------------------------------------------ -// Test module. -//------------------------------------------------------------------ module tb_montprod(); -//---------------------------------------------------------------- -// Internal constant and parameter definitions. -//---------------------------------------------------------------- - parameter SHOW_INIT = 0; - - parameter DUMP_MEM = 0; - parameter DEBUG = 0; + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- parameter CLK_HALF_PERIOD = 2; - parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; - - -//---------------------------------------------------------------- -// Register and Wire declarations. -//---------------------------------------------------------------- - -reg tb_clk; -reg tb_reset_n; -reg tb_calculate; -wire tb_ready; -reg [ 7 : 0] tb_length; -wire [ 7 : 0] tb_opa_addr; -reg [31 : 0] tb_opa_data; -wire [ 7 : 0] tb_opb_addr; -reg [31 : 0] tb_opb_data; -wire [ 7 : 0] tb_opm_addr; -reg [31 : 0] tb_opm_data; -wire [ 7 : 0] tb_result_addr; -wire [31 : 0] tb_result_data; -wire tb_result_we; - -reg [31 : 0] tb_a [0 : 255]; //tb_opa_data -reg [31 : 0] tb_b [0 : 255]; //tb_opb_data reads here -reg [31 : 0] tb_m [0 : 255]; //tb_opm_data reads here -reg [31 : 0] tb_r [0 : 255]; //tb_result_data writes here - - reg monitor_s; - -integer test_mont_prod_success; -integer test_mont_prod_fail; - -//---------------------------------------------------------------- -// Device Under Test. -//---------------------------------------------------------------- - -montprod dut( - .clk(tb_clk), - .reset_n(tb_reset_n), - .length(tb_length), - .calculate(tb_calculate), - .ready(tb_ready), - .opa_addr(tb_opa_addr), - .opa_data(tb_opa_data), - .opb_addr(tb_opb_addr), - .opb_data(tb_opb_data), - .opm_addr(tb_opm_addr), - .opm_data(tb_opm_data), - .result_addr(tb_result_addr), - .result_data(tb_result_data), - .result_we(tb_result_we) -); - -always @(posedge tb_clk) - begin : read_test_memory - tb_opa_data <= tb_a[tb_opa_addr]; - tb_opb_data <= tb_b[tb_opb_addr]; - tb_opm_data <= tb_m[tb_opm_addr]; - - if (DUMP_MEM) - $display("a %x %x b %x %x m %x %x", tb_opa_addr, tb_a[tb_opa_addr], tb_opb_addr, tb_b[tb_opb_addr], tb_opm_addr, tb_m[tb_opm_addr]); - end - -always @* - begin : write_test_memory - if (tb_result_we == 1'b1) - begin - $display("write %d: %x", tb_result_addr, tb_result_data); - tb_r[tb_result_addr] = tb_result_data; - end - end + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + parameter SHOW_INIT = 0; + parameter DUMP_MEM = 0; + parameter DEBUG = 0; + parameter SHOW_WRITE_MEM = 0; + parameter SHOW_WRITE_RESULT_MEM = 0; + parameter SHOW_S_MONITOR = 0; + parameter SHOW_BQ_DEBUG = 0; + parameter SHOW_FSM_STATUS = 0; + parameter DISPLAY_TEST_CYCLES = 1; + + parameter WAIT_TIMEOUT = 100000000; + + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg tb_clk; + reg tb_reset_n; + reg tb_calculate; + wire tb_ready; + reg [ 7 : 0] tb_length; + wire [ 7 : 0] tb_opa_addr; + reg [31 : 0] tb_opa_data; + wire [ 7 : 0] tb_opb_addr; + reg [31 : 0] tb_opb_data; + wire [ 7 : 0] tb_opm_addr; + reg [31 : 0] tb_opm_data; + wire [ 7 : 0] tb_result_addr; + wire [31 : 0] tb_result_data; + wire tb_result_we; + + reg [31 : 0] test_cycle_ctr; + reg test_cycle_ctr_rst; + reg test_cycle_ctr_inc; + + reg [31 : 0] tb_a [0 : 255]; //tb_opa_data + reg [31 : 0] tb_b [0 : 255]; //tb_opb_data reads here + reg [31 : 0] tb_m [0 : 255]; //tb_opm_data reads here + reg [31 : 0] tb_r [0 : 255]; //tb_result_data writes here + + integer test_mont_prod_success; + integer test_mont_prod_fail; + + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + montprod dut( + .clk(tb_clk), + .reset_n(tb_reset_n), + .length(tb_length), + .calculate(tb_calculate), + .ready(tb_ready), + .opa_addr(tb_opa_addr), + .opa_data(tb_opa_data), + .opb_addr(tb_opb_addr), + .opb_data(tb_opb_data), + .opm_addr(tb_opm_addr), + .opm_data(tb_opm_data), + .result_addr(tb_result_addr), + .result_data(tb_result_data), + .result_we(tb_result_we) + ); + + + //---------------------------------------------------------------- + // clk_gen + // Clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #CLK_HALF_PERIOD tb_clk = !tb_clk; + end // clk_gen + + + //---------------------------------------------------------------- + // test_cycle_counter + // + // Used to measure the number of cycles it takes to perform + // a given test case. + //---------------------------------------------------------------- + always @ (posedge tb_clk) + begin + if (test_cycle_ctr_rst) + test_cycle_ctr = 64'h0000000000000000; + if (test_cycle_ctr_inc) + test_cycle_ctr = test_cycle_ctr + 1; + end -//---------------------------------------------------------------- -// clk_gen -// -// Clock generator process. -//---------------------------------------------------------------- -always - begin : clk_gen - #CLK_HALF_PERIOD tb_clk = !tb_clk; - end // clk_gen + //---------------------------------------------------------------- + // start_test_cycle_ctr + // + // Reset and start the test cycle counter. + //---------------------------------------------------------------- + task start_test_cycle_ctr(); + begin + test_cycle_ctr_rst = 1; + #(CLK_PERIOD); + test_cycle_ctr_rst = 0; -//---------------------------------------------------------------- -// S monitor -//---------------------------------------------------------------- - always @ (posedge tb_clk) - begin : s_monitor - if (monitor_s) - $display("S[ 0 ]: %x", dut.s_mem.mem[0] ); + test_cycle_ctr_inc = 1; + end + endtask // start_test_cycle_ctr() + + + //---------------------------------------------------------------- + // stop_test_cycle_ctr() + // + // Stop the test cycle counter and optionally display the + // result. + //---------------------------------------------------------------- + task stop_test_cycle_ctr(); + begin + test_cycle_ctr_inc = 0; + #(CLK_PERIOD); + + if (DISPLAY_TEST_CYCLES) + $display("*** Number of cycles performed during test: 0x%016x", test_cycle_ctr); end + endtask // stop_test_cycle_ctr() + //---------------------------------------------------------------- + // read_test_memory + //---------------------------------------------------------------- + always @(posedge tb_clk) + begin : read_test_memory + tb_opa_data <= tb_a[tb_opa_addr]; + tb_opb_data <= tb_b[tb_opb_addr]; + tb_opm_data <= tb_m[tb_opm_addr]; -//---------------------------------------------------------------- -// S monitor -//---------------------------------------------------------------- - always @ (posedge tb_clk) - begin : s_write_minitor - if (monitor_s) - if (dut.s_mem_we) - $display("Write to S[0x%02x]: 0x%08x", dut.s_mem_wr_addr, dut.s_mem_new); + if (DUMP_MEM) + $display("a %x %x b %x %x m %x %x", tb_opa_addr, tb_a[tb_opa_addr], tb_opb_addr, tb_b[tb_opb_addr], tb_opm_addr, tb_m[tb_opm_addr]); end + //---------------------------------------------------------------- + // write_result_memory + //---------------------------------------------------------------- + always @* + begin : write_result_memory + if (tb_result_we == 1'b1) + begin + tb_r[tb_result_addr] = tb_result_data; + + if (SHOW_WRITE_RESULT_MEM) + $display("write result mnen 0x%02%x: 0x%08x", tb_result_addr, tb_result_data); + end + end -//---------------------------------------------------------------- -//---------------------------------------------------------------- + + //---------------------------------------------------------------- + // s_monitor + //---------------------------------------------------------------- + always @ (posedge tb_clk) + begin : s_monitor + if (SHOW_S_MONITOR) + begin + $display("S[0x00]: 0x%08x", dut.s_mem.mem[0]); + + if (dut.s_mem_we_reg) + $display("Write to S[0x%02x]: 0x%08x", dut.s_mem_write_addr, dut.s_mem_write_data); + end + end + + + //---------------------------------------------------------------- + // bq_debug + //---------------------------------------------------------------- always @ (posedge tb_clk) begin : bq_debug - if (dut.montprod_ctrl_reg == dut.CTRL_L_CALC_SM) - $display("====================> B: %x Q: %x B_bit_index_reg: %x <=====================", dut.b_reg, dut.q_reg, dut.B_bit_index_reg); + if (SHOW_BQ_DEBUG) + begin + if (dut.montprod_ctrl_reg == dut.CTRL_CALC_ADD) + $display("====================> B: %x Q: %x b_bit_index_reg: %x <=====================", dut.b_reg, dut.q_reg, dut.b_bit_index_reg); + end end - //case (montprod_ctrl_reg) - // CTRL_LOOP_BQ: - // $display("DEBUG: b: %d q: %d opa_data %x opb_data %x s_mem_read_data %x", b, q, opa_addr_reg, opa_data, opb_data, s_mem_read_data); - // default: - // begin end - //endcase -//---------------------------------------------------------------- -//---------------------------------------------------------------- + //---------------------------------------------------------------- + // fsm_monitor + //---------------------------------------------------------------- always @ (posedge tb_clk) - begin : fsm_debug - if (dut.montprod_ctrl_we) - case (dut.montprod_ctrl_new) - dut.CTRL_IDLE: - $display("FSM: IDLE"); - dut.CTRL_INIT_S: - $display("FSM: INIT_S"); - dut.CTRL_LOOP_INIT: - $display("FSM: LOOP_INIT"); - dut.CTRL_LOOP_ITER: - $display("FSM: LOOP_ITER"); - dut.CTRL_LOOP_BQ: - $display("FSM: LOOP_BQ"); - dut.CTRL_L_CALC_SM: - $display("FSM: LOOP_CALC_SM"); - dut.CTRL_L_CALC_SA: - $display("FSM: LOOP_CALC_SA"); - dut.CTRL_L_STALLPIPE_SA: - $display("FSM: STALL_PIPE"); - dut.CTRL_L_CALC_SDIV2: - $display("FSM: LOOP_CALC_SDIV2"); - dut.CTRL_EMIT_S: - $display("FSM: LOOP_EMIT_S"); - dut.CTRL_DONE: - $display("FSM: DONE"); - default: - $display("FSM: %x", dut.montprod_ctrl_new); - endcase + begin : fsm_monitor + if (SHOW_FSM_STATUS) + if (dut.montprod_ctrl_we) + case (dut.montprod_ctrl_new) + dut.CTRL_IDLE: + $display("FSM: IDLE"); + dut.CTRL_LOOP_ITER: + $display("FSM: LOOP_ITER"); + dut.CTRL_LOOP_BQ: + $display("FSM: LOOP_BQ"); + dut.CTRL_CALC_ADD: + $display("FSM: LOOP_CALC_ADD"); + dut.CTRL_STALLPIPE_ADD: + $display("FSM: STALL_PIPE_ADD"); + dut.CTRL_CALC_SDIV2: + $display("FSM: CALC_SDIV2"); + dut.CTRL_EMIT_S: + $display("FSM: LOOP_EMIT_S"); + default: + $display("FSM: %x", dut.montprod_ctrl_new); + endcase end -//---------------------------------------------------------------- -// reset_dut() -// -// Toggles reset to force the DUT into a well defined state. -//---------------------------------------------------------------- -task reset_dut(); - begin - $display("*** Toggle reset."); - tb_reset_n = 0; - #(2 * CLK_PERIOD); - tb_reset_n = 1; - end -endtask // reset_dut - -//---------------------------------------------------------------- -// init_sim() -// -// Initialize all counters and testbed functionality as well -// as setting the DUT inputs to defined values. -//---------------------------------------------------------------- -task init_sim(); - begin - $display("*** init_sim"); - tb_clk = 0; - tb_reset_n = 0; - tb_length = 0; - tb_calculate = 0; - monitor_s = 1; - test_mont_prod_success = 0; - test_mont_prod_fail = 0; - end -endtask // init_dut - -//---------------------------------------------------------------- -// wait_ready() -// -// Wait for the ready flag in the dut to be set. -// -// Note: It is the callers responsibility to call the function -// when the dut is actively processing and will in fact at some -// point set the flag. -//---------------------------------------------------------------- -task wait_ready(); - begin - $display("*** wait_ready"); - begin: wait_loop - integer i; - for (i=0; i<1000000; i=i+1) - if (tb_ready == 0) - #(CLK_PERIOD); + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut(); + begin + $display("*** Toggle reset."); + tb_reset_n = 0; + #(2 * CLK_PERIOD); + tb_reset_n = 1; + end + endtask // reset_dut + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim(); + begin + $display("*** init_sim"); + tb_clk = 0; + tb_reset_n = 0; + tb_length = 0; + tb_calculate = 0; + test_mont_prod_success = 0; + test_mont_prod_fail = 0; end - if (tb_ready == 0) - begin - $display("*** wait_ready failed, never became ready!"); - $finish; - end - end -endtask // wait_ready - -//---------------------------------------------------------------- -//---------------------------------------------------------------- -task signal_calculate(); - begin - $display("*** signal_calculate"); - tb_calculate = 1; - #(CLK_PERIOD); - tb_calculate = 0; - end -endtask // signal_calculate - - -//---------------------------------------------------------------- -// Tests the montgomery multiplications -//---------------------------------------------------------------- -task test_mont_prod( - input [7 : 0] length, - input [0 : 8192-1] a, - input [0 : 8192-1] b, - input [0 : 8192-1] m, - input [0 : 8192-1] expected - ); - begin - $display("*** test started"); - begin: copy_test_vectors + endtask // init_sim + + + //---------------------------------------------------------------- + // wait_ready() + // + // Wait for the ready flag in the dut to be set. + // + // Note: It is the callers responsibility to call the function + // when the dut is actively processing and will in fact at some + // point set the flag. + //---------------------------------------------------------------- + task wait_ready(); + begin : wait_ready integer i; - integer j; - $display("*** Initializing..."); - for (i=32'h0; i<256; i=i+1) + $display("*** waiting for core to be ready..."); + + i = 0; + while ((tb_ready == 0) && (i < WAIT_TIMEOUT)) begin - j = {i, 5'h0}; - tb_a[i] = a[j +: 32]; - tb_b[i] = b[j +: 32]; - tb_m[i] = m[j +: 32]; - tb_r[i] = 32'h0; - if (SHOW_INIT) - $display("*** init %0x: a: %x b: %x m: %x r: %x", i, tb_a[i], tb_b[i], tb_m[i], tb_r[i]); + i = i + 1; + #(CLK_PERIOD); end - end - $display("*** Test vector copied"); - wait_ready(); - tb_length = length; - signal_calculate(); - wait_ready(); - begin: verify_test_vectors - integer i; - integer j; - integer success; - integer fail; - success = 1; - fail = 0; - for (i=0; i<length; i=i+1) + if (tb_ready == 0) begin - j = i * 32; - $display("offset: %02d expected 0x%08x actual 0x%08x", i, expected[j +: 32], tb_r[i]); - if (expected[j +: 32] != tb_r[i]) - begin - success = 0; - fail = 1; - end + $display("*** wait_ready failed, never became ready!"); + $finish; end - test_mont_prod_success = test_mont_prod_success + success; - test_mont_prod_fail = test_mont_prod_fail + fail; end + endtask // wait_ready + + + //---------------------------------------------------------------- + // signal_calculate() + // + // Start the montgomery calculation by pulling the calculate + // flag to the dut. + //---------------------------------------------------------------- + task signal_calculate(); + begin + $display("*** signal_calculate"); + tb_calculate = 1; + #(CLK_PERIOD); + tb_calculate = 0; + end + endtask // signal_calculate + + + //---------------------------------------------------------------- + // Tests the montgomery multiplications + //---------------------------------------------------------------- + task test_mont_prod( + input [7 : 0] length, + input [0 : 8192-1] a, + input [0 : 8192-1] b, + input [0 : 8192-1] m, + input [0 : 8192-1] expected + ); + begin + $display("*** Mongomry multiplier test started"); + begin: copy_test_vectors + integer i; + integer j; + + $display("*** Initializing..."); + for (i=32'h0; i<256; i=i+1) + begin + j = {i, 5'h0}; + tb_a[i] = a[j +: 32]; + tb_b[i] = b[j +: 32]; + tb_m[i] = m[j +: 32]; + tb_r[i] = 32'h0; + if (SHOW_INIT) + $display("*** init %0x: a: %x b: %x m: %x r: %x", i, tb_a[i], tb_b[i], tb_m[i], tb_r[i]); + end + end + + $display("*** Test vector copied"); + wait_ready(); + tb_length = length; + + start_test_cycle_ctr(); + + signal_calculate(); + wait_ready(); + + stop_test_cycle_ctr(); + + begin: verify_test_vectors + integer i; + integer j; + integer success; + integer fail; + success = 1; + fail = 0; + for (i=0; i<length; i=i+1) + begin + j = i * 32; + $display("offset: %02d expected 0x%08x actual 0x%08x", i, expected[j +: 32], tb_r[i]); + if (expected[j +: 32] != tb_r[i]) + begin + success = 0; + fail = 1; + end + end + test_mont_prod_success = test_mont_prod_success + success; + test_mont_prod_fail = test_mont_prod_fail + fail; + + if (success) + $display("*** test stopped, test successful."); + else + $display("*** test stopped, test failed."); + $display(""); + end + end + endtask // test_mont_prod + + + //---------------------------------------------------------------- + // short_tests + // + // Short tests that are fast to run jut to check that the + // functionality is as expected. + //---------------------------------------------------------------- + task short_tests(); + begin : short_tests + //* A= b B= 11 M= 13 A*B= 10 Ar= 9 Br= 7 Ar*Br= 1 A*B= 10 + + test_mont_prod( 1, {32'h9, 8160'h0}, {32'h7, 8160'h0}, {32'h13,8160'h0}, {32'h1,8160'h0} ); + + //* A= b B= 13 M= 11 A*B= 5 Ar= b Br= 2 Ar*Br= 5 A*B= 5 + + test_mont_prod( 1, {32'hb, 8160'h0}, {32'h2, 8160'h0}, {32'h11,8160'h0}, {32'h5,8160'h0} ); + + //* A= 11 B= b M= 13 A*B= 10 Ar= 7 Br= 9 Ar*Br= 1 A*B= 10 + + test_mont_prod( 1, {32'h7, 8160'h0}, {32'h9, 8160'h0}, {32'h13,8160'h0}, {32'h1,8160'h0} ); + + //* A= 11 B= 13 M= b A*B= 4 Ar= 2 Br= a Ar*Br= 5 A*B= 4 + + test_mont_prod( 1, {32'h2, 8160'h0}, {32'ha, 8160'h0}, {32'h0b,8160'h0}, {32'h5,8160'h0} ); + + //* A= 13 B= b M= 11 A*B= 5 Ar= 2 Br= b Ar*Br= 5 A*B= 5 + //* A= 13 B= 11 M= b A*B= 4 Ar= a Br= 2 Ar*Br= 5 A*B= 4 + //* A=10001 B= 11 M= 13 A*B= 7 Ar= 11 Br= 7 Ar*Br= 4 A*B= 7 + //* A=10001 B= 13 M= 11 A*B= 4 Ar= 2 Br= 2 Ar*Br= 4 A*B= 4 + //* A= 11 B=10001 M= 13 A*B= 7 Ar= 7 Br= 11 Ar*Br= 4 A*B= 7 + //* A= 11 B= 13 M=10001 A*B=143 Ar= 11 Br= 13 Ar*Br=143 A*B=143 + //* A= 13 B=10001 M= 11 A*B= 4 Ar= 2 Br= 2 Ar*Br= 4 A*B= 4 + //* A= 13 B= 11 M=10001 A*B=143 Ar= 13 Br= 11 Ar*Br=143 A*B=143 + //* A=10001 B= 11 M=7fffffff A*B=110011 Ar=20002 Br= 22 Ar*Br=220022 A*B=110011 + //* A=10001 B=7fffffff M= 11 A*B= 10 Ar= 2 Br= 8 Ar*Br= 10 A*B= 10 + //* A= 11 B=10001 M=7fffffff A*B=110011 Ar= 22 Br=20002 Ar*Br=220022 A*B=110011 + //* A= 11 B=7fffffff M=10001 A*B=7ff8 Ar= 11 Br=8000 Ar*Br=7ff8 A*B=7ff8 + //* A=7fffffff B=10001 M= 11 A*B= 10 Ar= 8 Br= 2 Ar*Br= 10 A*B= 10 + //* A=7fffffff B= 11 M=10001 A*B=7ff8 Ar=8000 Br= 11 Ar*Br=7ff8 A*B=7ff8 + + //debug A => 0 0 1 + //debug B => 0 0 4000 + //debug M => 1ffffff ffffffff ffffffff + //debug s => 0 0 80 + test_mont_prod( 3, {96'h1, 8096'h0}, {96'h4000, 8096'h0}, {96'h1ffffffffffffffffffffff,8096'h0}, {96'h80,8096'h0} ); + end + endtask // short_tests + + + //---------------------------------------------------------------- + // long_tests() + // + // Longer, tests with real operand sizes. + //---------------------------------------------------------------- + task long_tests(); + begin + //debug A => 00000000 098b0437 ae647838 09d930b9 a1d269d5 03579a63 9c4e3ac5 fd070836 413389c2 321cfe8b a6a5732e bc7cbcf8 a2f1df87 19f7a767 43ef9b5d 6bd33597 23bfc574 8ec046da 5419d7ff 31811123 740b227b 709f3ace e53ba5cc 38cbc161 a0c15c88 64f26a18 423692ef a5e52a20 80d9f244 717aa2d5 e1a6680a b29eed64 57c6b005 + //debug B => 00000000 098b0437 ae647838 09d930b9 a1d269d5 03579a63 9c4e3ac5 fd070836 413389c2 321cfe8b a6a5732e bc7cbcf8 a2f1df87 19f7a767 43ef9b5d 6bd33597 23bfc574 8ec046da 5419d7ff 31811123 740b227b 709f3ace e53ba5cc 38cbc161 a0c15c88 64f26a18 423692ef a5e52a20 80d9f244 717aa2d5 e1a6680a b29eed64 57c6b005 + //debug M => 00000000 f14b5a0a 122ff247 85813db2 02c0d3af bd0a4615 2889ff7d 8f655e9e c866e586 f21003a0 e969769b 127ec8a5 67f07708 217775f7 7654cabc 3a624f9b 4074bdf1 55fa84c0 0354fe59 0ad04cfd 14e666c0 ce6cea72 788c31f4 edcf3dd7 3a5a59c1 b9b3ef41 565df033 69a82de8 f18c2793 0abd5502 f3730ec0 d1943dc4 a660a267 + //debug s => 00000000 0a8a4a44 40e5c3b0 a05383c2 4ad92fc9 0af7b72e d22fa180 f3a99e64 38ffbe72 3854bc5e 93fffa55 ce49b2cf f809c9eb 81176d8b 4f8b942c 3de18f9c 6393a70a 89924a58 5684cb90 acfd1bde b408b2c0 a8d862c1 74b5a10d 90532d4e 79fe2f50 430decda 0ed75e0a ac354c46 69ce0bd8 eb36e857 b55623d1 527b9711 86cd4d75 + + test_mont_prod(33, + { 1056'h098b0437ae64783809d930b9a1d269d503579a639c4e3ac5fd070836413389c2321cfe8ba6a5732ebc7cbcf8a2f1df8719f7a76743ef9b5d6bd3359723bfc5748ec046da5419d7ff31811123740b227b709f3acee53ba5cc38cbc161a0c15c8864f26a18423692efa5e52a2080d9f244717aa2d5e1a6680ab29eed6457c6b005 + , 7136'h0 }, + { 1056'h098b0437ae64783809d930b9a1d269d503579a639c4e3ac5fd070836413389c2321cfe8ba6a5732ebc7cbcf8a2f1df8719f7a76743ef9b5d6bd3359723bfc5748ec046da5419d7ff31811123740b227b709f3acee53ba5cc38cbc161a0c15c8864f26a18423692efa5e52a2080d9f244717aa2d5e1a6680ab29eed6457c6b005 + , 7136'h0 }, + {1056'hf14b5a0a122ff24785813db202c0d3afbd0a46152889ff7d8f655e9ec866e586f21003a0e969769b127ec8a567f07708217775f77654cabc3a624f9b4074bdf155fa84c00354fe590ad04cfd14e666c0ce6cea72788c31f4edcf3dd73a5a59c1b9b3ef41565df03369a82de8f18c27930abd5502f3730ec0d1943dc4a660a267 + , 7136'h0 }, + {1056'h0a8a4a4440e5c3b0a05383c24ad92fc90af7b72ed22fa180f3a99e6438ffbe723854bc5e93fffa55ce49b2cff809c9eb81176d8b4f8b942c3de18f9c6393a70a89924a585684cb90acfd1bdeb408b2c0a8d862c174b5a10d90532d4e79fe2f50430decda0ed75e0aac354c4669ce0bd8eb36e857b55623d1527b971186cd4d75 + , 7136'h0 }); - $display("*** test stopped"); - end -endtask - -//---------------------------------------------------------------- -// The main test functionality. -//---------------------------------------------------------------- -initial - begin : montgomery_product_tests - $display(" -- Testbench for montprod started --"); - init_sim(); - reset_dut(); - -//* A= b B= 11 M= 13 A*B= 10 Ar= 9 Br= 7 Ar*Br= 1 A*B= 10 - - test_mont_prod( 1, {32'h9, 8160'h0}, {32'h7, 8160'h0}, {32'h13,8160'h0}, {32'h1,8160'h0} ); - -//* A= b B= 13 M= 11 A*B= 5 Ar= b Br= 2 Ar*Br= 5 A*B= 5 - - test_mont_prod( 1, {32'hb, 8160'h0}, {32'h2, 8160'h0}, {32'h11,8160'h0}, {32'h5,8160'h0} ); - -//* A= 11 B= b M= 13 A*B= 10 Ar= 7 Br= 9 Ar*Br= 1 A*B= 10 - - test_mont_prod( 1, {32'h7, 8160'h0}, {32'h9, 8160'h0}, {32'h13,8160'h0}, {32'h1,8160'h0} ); - -//* A= 11 B= 13 M= b A*B= 4 Ar= 2 Br= a Ar*Br= 5 A*B= 4 - - test_mont_prod( 1, {32'h2, 8160'h0}, {32'ha, 8160'h0}, {32'h0b,8160'h0}, {32'h5,8160'h0} ); - -//* A= 13 B= b M= 11 A*B= 5 Ar= 2 Br= b Ar*Br= 5 A*B= 5 -//* A= 13 B= 11 M= b A*B= 4 Ar= a Br= 2 Ar*Br= 5 A*B= 4 -//* A=10001 B= 11 M= 13 A*B= 7 Ar= 11 Br= 7 Ar*Br= 4 A*B= 7 -//* A=10001 B= 13 M= 11 A*B= 4 Ar= 2 Br= 2 Ar*Br= 4 A*B= 4 -//* A= 11 B=10001 M= 13 A*B= 7 Ar= 7 Br= 11 Ar*Br= 4 A*B= 7 -//* A= 11 B= 13 M=10001 A*B=143 Ar= 11 Br= 13 Ar*Br=143 A*B=143 -//* A= 13 B=10001 M= 11 A*B= 4 Ar= 2 Br= 2 Ar*Br= 4 A*B= 4 -//* A= 13 B= 11 M=10001 A*B=143 Ar= 13 Br= 11 Ar*Br=143 A*B=143 -//* A=10001 B= 11 M=7fffffff A*B=110011 Ar=20002 Br= 22 Ar*Br=220022 A*B=110011 -//* A=10001 B=7fffffff M= 11 A*B= 10 Ar= 2 Br= 8 Ar*Br= 10 A*B= 10 -//* A= 11 B=10001 M=7fffffff A*B=110011 Ar= 22 Br=20002 Ar*Br=220022 A*B=110011 -//* A= 11 B=7fffffff M=10001 A*B=7ff8 Ar= 11 Br=8000 Ar*Br=7ff8 A*B=7ff8 -//* A=7fffffff B=10001 M= 11 A*B= 10 Ar= 8 Br= 2 Ar*Br= 10 A*B= 10 -//* A=7fffffff B= 11 M=10001 A*B=7ff8 Ar=8000 Br= 11 Ar*Br=7ff8 A*B=7ff8 - - //debug A => 0 0 1 - //debug B => 0 0 4000 - //debug M => 1ffffff ffffffff ffffffff - //debug s => 0 0 80 - test_mont_prod( 3, {96'h1, 8096'h0}, {96'h4000, 8096'h0}, {96'h1ffffffffffffffffffffff,8096'h0}, {96'h80,8096'h0} ); - - //debug A => 00000000 098b0437 ae647838 09d930b9 a1d269d5 03579a63 9c4e3ac5 fd070836 413389c2 321cfe8b a6a5732e bc7cbcf8 a2f1df87 19f7a767 43ef9b5d 6bd33597 23bfc574 8ec046da 5419d7ff 31811123 740b227b 709f3ace e53ba5cc 38cbc161 a0c15c88 64f26a18 423692ef a5e52a20 80d9f244 717aa2d5 e1a6680a b29eed64 57c6b005 - //debug B => 00000000 098b0437 ae647838 09d930b9 a1d269d5 03579a63 9c4e3ac5 fd070836 413389c2 321cfe8b a6a5732e bc7cbcf8 a2f1df87 19f7a767 43ef9b5d 6bd33597 23bfc574 8ec046da 5419d7ff 31811123 740b227b 709f3ace e53ba5cc 38cbc161 a0c15c88 64f26a18 423692ef a5e52a20 80d9f244 717aa2d5 e1a6680a b29eed64 57c6b005 - //debug M => 00000000 f14b5a0a 122ff247 85813db2 02c0d3af bd0a4615 2889ff7d 8f655e9e c866e586 f21003a0 e969769b 127ec8a5 67f07708 217775f7 7654cabc 3a624f9b 4074bdf1 55fa84c0 0354fe59 0ad04cfd 14e666c0 ce6cea72 788c31f4 edcf3dd7 3a5a59c1 b9b3ef41 565df033 69a82de8 f18c2793 0abd5502 f3730ec0 d1943dc4 a660a267 - //debug s => 00000000 0a8a4a44 40e5c3b0 a05383c2 4ad92fc9 0af7b72e d22fa180 f3a99e64 38ffbe72 3854bc5e 93fffa55 ce49b2cf f809c9eb 81176d8b 4f8b942c 3de18f9c 6393a70a 89924a58 5684cb90 acfd1bde b408b2c0 a8d862c1 74b5a10d 90532d4e 79fe2f50 430decda 0ed75e0a ac354c46 69ce0bd8 eb36e857 b55623d1 527b9711 86cd4d75 - - test_mont_prod( - 33, -{ 1056'h098b0437ae64783809d930b9a1d269d503579a639c4e3ac5fd070836413389c2321cfe8ba6a5732ebc7cbcf8a2f1df8719f7a76743ef9b5d6bd3359723bfc5748ec046da5419d7ff31811123740b227b709f3acee53ba5cc38cbc161a0c15c8864f26a18423692efa5e52a2080d9f244717aa2d5e1a6680ab29eed6457c6b005 -, 7136'h0 }, -{ 1056'h098b0437ae64783809d930b9a1d269d503579a639c4e3ac5fd070836413389c2321cfe8ba6a5732ebc7cbcf8a2f1df8719f7a76743ef9b5d6bd3359723bfc5748ec046da5419d7ff31811123740b227b709f3acee53ba5cc38cbc161a0c15c8864f26a18423692efa5e52a2080d9f244717aa2d5e1a6680ab29eed6457c6b005 -, 7136'h0 }, -{1056'hf14b5a0a122ff24785813db202c0d3afbd0a46152889ff7d8f655e9ec866e586f21003a0e969769b127ec8a567f07708217775f77654cabc3a624f9b4074bdf155fa84c00354fe590ad04cfd14e666c0ce6cea72788c31f4edcf3dd73a5a59c1b9b3ef41565df03369a82de8f18c27930abd5502f3730ec0d1943dc4a660a267 -, 7136'h0 }, -{1056'h0a8a4a4440e5c3b0a05383c24ad92fc90af7b72ed22fa180f3a99e6438ffbe723854bc5e93fffa55ce49b2cff809c9eb81176d8b4f8b942c3de18f9c6393a70a89924a585684cb90acfd1bdeb408b2c0a8d862c174b5a10d90532d4e79fe2f50430decda0ed75e0aac354c4669ce0bd8eb36e857b55623d1527b971186cd4d75 -, 7136'h0 }); - - $display(" -- Testbench for montprod done. --"); - $display(" tests success: %d", test_mont_prod_success); - $display(" tests failed: %d", test_mont_prod_fail); - $finish; - end // montprod + end + endtask // long_tests + + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + initial + begin : montgomery_product_tests + $display(" -- Testbench for montprod started --"); + init_sim(); + reset_dut(); + + short_tests(); +// long_tests(); + + $display(" -- Testbench for montprod done. --"); + $display(" tests success: %d", test_mont_prod_success); + $display(" tests failed: %d", test_mont_prod_fail); + $finish; + end // montprod endmodule // tb_montprod //====================================================================== |