3 files changed, 3 insertions, 3 deletions
diff --git a/src/rtl/blockmem2r1w.v b/src/rtl/blockmem2r1w.v
index 557e810..aa44101 100644
--- a/src/rtl/blockmem2r1w.v
+++ b/src/rtl/blockmem2r1w.v
@@ -54,7 +54,7 @@ module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8)
                     input wire  [(OPW - 1) : 0] write_data
                    );
 
-  reg [(OPW - 1) : 0] mem [0 :  (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
   reg [(OPW - 1) : 0] tmp_read_data0;
   reg [(OPW - 1) : 0] tmp_read_data1;
 
diff --git a/src/rtl/blockmem2r1wptr.v b/src/rtl/blockmem2r1wptr.v
index b9abfa8..2435cfd 100644
--- a/src/rtl/blockmem2r1wptr.v
+++ b/src/rtl/blockmem2r1wptr.v
@@ -67,7 +67,7 @@ module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8)
   //----------------------------------------------------------------
   // Memories and regs including update variables and write enable.
   //----------------------------------------------------------------
-  reg [(OPW - 1) : 0] mem [0 :  (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
   reg [(OPW - 1) : 0] tmp_read_data0;
   reg [31 : 0]        tmp_read_data1;
 
diff --git a/src/rtl/blockmem2rptr1w.v b/src/rtl/blockmem2rptr1w.v
index fc7d83a..a1d7448 100644
--- a/src/rtl/blockmem2rptr1w.v
+++ b/src/rtl/blockmem2rptr1w.v
@@ -65,7 +65,7 @@ module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
   //----------------------------------------------------------------
   // Memories and regs including update variables and write enable.
   //----------------------------------------------------------------
-  reg [(OPW - 1) : 0] mem [0 :  (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
   reg [(OPW - 1) : 0] tmp_read_data0;
   reg [31 : 0]        tmp_read_data1;