diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/montprod.v | 43 |
1 files changed, 20 insertions, 23 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v index 7276b4b..4af1069 100644 --- a/src/rtl/montprod.v +++ b/src/rtl/montprod.v @@ -87,13 +87,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- - reg [(ADW - 1) : 0] opa_addr_reg; - reg [(ADW - 1) : 0] opb_addr_reg; - reg [(ADW - 1) : 0] opm_addr_reg; - - reg [(ADW - 1) : 0] result_addr_reg; - reg [(OPW - 1) : 0] result_data_reg; - reg ready_reg; reg ready_new; reg ready_we; @@ -139,8 +132,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) reg inc_word_index; reg dec_word_index; - reg [(ADW - 1) : 0] length_m1; - reg add_carry_in_sa_reg; reg add_carry_in_sa_new; reg add_carry_in_sm_reg; @@ -157,7 +148,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - reg tmp_result_we; wire [(OPW - 1) : 0] add_result_sa; wire add_carry_out_sa; wire [(OPW - 1) : 0] add_result_sm; @@ -167,10 +157,18 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) wire shr_carry_out; wire [(OPW - 1) : 0] shr_data_out; + reg [(ADW - 1) : 0] tmp_opa_addr; + reg [(ADW - 1) : 0] tmp_opb_addr; + reg [(ADW - 1) : 0] tmp_opm_addr; + reg [(ADW - 1) : 0] tmp_result_addr; + reg [(OPW - 1) : 0] tmp_result_data; + reg tmp_result_we; reg [(OPW - 1) : 0] sa_adder_data_in; reg [(OPW - 1) : 0] muxed_s_mem_read_data; + reg [(ADW - 1) : 0] length_m1; + // Temporary debug wires. reg b_js; reg pr_tt; @@ -179,12 +177,12 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign opa_addr = opa_addr_reg; - assign opb_addr = opb_addr_reg; - assign opm_addr = opm_addr_reg; + assign opa_addr = tmp_opa_addr; + assign opb_addr = tmp_opb_addr; + assign opm_addr = tmp_opm_addr; - assign result_addr = result_addr_reg; - assign result_data = result_data_reg; + assign result_addr = tmp_result_addr; + assign result_data = tmp_result_data; assign result_we = tmp_result_we; assign ready = ready_reg; @@ -303,17 +301,16 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) //---------------------------------------------------------------- always @* begin : prodcalc - opa_addr_reg = word_index_reg; - opb_addr_reg = b_word_index; - opm_addr_reg = word_index_reg; - tmp_result_we = 1'b0; - - result_addr_reg = word_index_prev_reg; - result_data_reg = s_mem_read_data; + tmp_opa_addr = word_index_reg; + tmp_opb_addr = b_word_index; + tmp_opm_addr = word_index_reg; + tmp_result_addr = word_index_prev_reg; + tmp_result_data = s_mem_read_data; + tmp_result_we = 1'b0; if (montprod_ctrl_reg == CTRL_LOOP_ITER) begin - opa_addr_reg = length_m1; + tmp_opa_addr = length_m1; end if (montprod_ctrl_reg == CTRL_EMIT_S) |