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Diffstat (limited to 'src/rtl/shr32.v')
-rw-r--r-- | src/rtl/shr32.v | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/rtl/shr32.v b/src/rtl/shr32.v new file mode 100644 index 0000000..840f9df --- /dev/null +++ b/src/rtl/shr32.v @@ -0,0 +1,53 @@ +//====================================================================== +// +// shr32.v +// --------- +// 32bit shifter with carry in / carry out +// +// +// Author: Peter Magnusson +// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + + +module shr32( + input [31 : 0] a, + input carry_in, + output wire [31 : 0] adiv2, + output wire carry_out); + + reg [32 : 0] shr_result; + + assign adiv2 = shr_result[32:1]; + assign carry_out = shr_result[0]; + + always @(a, carry_in) + shr_result = { carry_in, a }; +endmodule |