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-rw-r--r--src/rtl/montprod.v64
1 files changed, 32 insertions, 32 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 465fa38..ffee748 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -186,38 +186,38 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
- blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
- .clk(clk),
- .read_addr(s_mem_addr),
- .read_data(s_mem_read_data),
- .wr(s_mem_we_reg),
- .write_addr(s_mem_wr_addr_reg),
- .write_data(s_mem_new)
- );
-
- adder32 s_adder_sm(
- .a(muxed_s_mem_read_data),
- .b(opm_data),
- .carry_in(add_carry_in_sm_reg),
- .sum(add_result_sm),
- .carry_out(add_carry_out_sm)
- );
-
-
- adder32 s_adder_sa(
- .a(sa_adder_data_in),
- .b(opa_data),
- .carry_in(add_carry_in_sa_reg),
- .sum(add_result_sa),
- .carry_out(add_carry_out_sa)
- );
-
- shr32 shifter(
- .a(s_mem_read_data),
- .carry_in(shr_carry_in_reg),
- .adiv2(shr_data_out),
- .carry_out(shr_carry_out)
- );
+ blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
+ .clk(clk),
+ .read_addr(s_mem_addr),
+ .read_data(s_mem_read_data),
+ .wr(s_mem_we_reg),
+ .write_addr(s_mem_wr_addr_reg),
+ .write_data(s_mem_new)
+ );
+
+ adder #(.OPW(OPW)) s_adder_sm(
+ .a(muxed_s_mem_read_data),
+ .b(opm_data),
+ .carry_in(add_carry_in_sm_reg),
+ .sum(add_result_sm),
+ .carry_out(add_carry_out_sm)
+ );
+
+
+ adder #(.OPW(OPW)) s_adder_sa(
+ .a(sa_adder_data_in),
+ .b(opa_data),
+ .carry_in(add_carry_in_sa_reg),
+ .sum(add_result_sa),
+ .carry_out(add_carry_out_sa)
+ );
+
+ shr #(.OPW(OPW)) shifter(
+ .a(s_mem_read_data),
+ .carry_in(shr_carry_in_reg),
+ .adiv2(shr_data_out),
+ .carry_out(shr_carry_out)
+ );
//----------------------------------------------------------------