diff options
Diffstat (limited to 'src/rtl/blockmem2r1wptr.v')
| -rw-r--r-- | src/rtl/blockmem2r1wptr.v | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/src/rtl/blockmem2r1wptr.v b/src/rtl/blockmem2r1wptr.v index 41efc85..2435cfd 100644 --- a/src/rtl/blockmem2r1wptr.v +++ b/src/rtl/blockmem2r1wptr.v @@ -8,6 +8,12 @@ // when the cs signal is set. The pointer is reset to zero when // the rst signal is asserted. // +// +// NOTE: This memory needs to be rebuilt if interface 0 is changed +// to use bigger operand widths and fewer words than interface 1. +// This adaption is NOT automatic. +// +// // The memory is used in the modexp core. // // @@ -42,32 +48,32 @@ // //====================================================================== -module blockmem2r1wptr( - input wire clk, - input wire reset_n, - - input wire [07 : 0] read_addr0, - output wire [31 : 0] read_data0, +module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8) + ( + input wire clk, + input wire reset_n, - output wire [31 : 0] read_data1, + input wire [(ADW - 1) : 0] read_addr0, + output wire [(OPW - 1) : 0] read_data0, - input wire rst, - input wire cs, - input wire wr, - input wire [31 : 0] write_data + output wire [31 : 0] read_data1, + input wire rst, + input wire cs, + input wire wr, + input wire [31 : 0] write_data ); //---------------------------------------------------------------- // Memories and regs including update variables and write enable. //---------------------------------------------------------------- - reg [31 : 0] mem [0 : 255]; - reg [31 : 0] tmp_read_data0; - reg [31 : 0] tmp_read_data1; + reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)]; + reg [(OPW - 1) : 0] tmp_read_data0; + reg [31 : 0] tmp_read_data1; - reg [7 : 0] ptr_reg; - reg [7 : 0] ptr_new; - reg ptr_we; + reg [7 : 0] ptr_reg; + reg [7 : 0] ptr_new; + reg ptr_we; //---------------------------------------------------------------- @@ -94,10 +100,10 @@ module blockmem2r1wptr( //---------------------------------------------------------------- - // reg_update + // ptr_update //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) - begin : reg_mem_update + begin : ptr_update if (!reset_n) ptr_reg <= 8'h00; |