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+//======================================================================
+//
+// adder.v
+// -------
+// Adder with separate carry in and carry out. Used in the montprod
+// amd residue modules of the modexp core.
+//
+//
+// Author: Peter Magnusson, Joachim Strömbergson
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module adder #(parameter OPW = 32)
+              (
+               input      [(OPW - 1) : 0]  a,
+               input      [(OPW - 1) : 0]  b,
+               input                       carry_in,
+
+               output wire [(OPW - 1) : 0] sum,
+               output wire                 carry_out
+              );
+
+  reg [(OPW) : 0] adder_result;
+
+   assign sum = adder_result[(OPW - 1) : 0];
+   assign carry_out = adder_result[(OPW)];
+
+   always @*
+     begin
+       adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in};
+     end
+
+endmodule // adder
+
+//======================================================================
+// EOF adder.v
+//======================================================================