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-rw-r--r--src/rtl/modexp_core.v14
-rw-r--r--src/tb/tb_modexp.v61
-rw-r--r--src/tb/tb_modexp_autogenerated.v4
3 files changed, 66 insertions, 13 deletions
diff --git a/src/rtl/modexp_core.v b/src/rtl/modexp_core.v
index 45d1aa9..c1a88d1 100644
--- a/src/rtl/modexp_core.v
+++ b/src/rtl/modexp_core.v
@@ -236,7 +236,8 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
reg residue_valid_new;
reg residue_valid_int_validated;
- wire [7 : 0] length_m1;
+ wire [7 : 0] modulus_length_m1;
+ wire [7 : 0] exponent_length_m1;
//----------------------------------------------------------------
@@ -245,7 +246,8 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
assign ready = ready_reg;
assign cycles = {cycle_ctr_high_reg, cycle_ctr_low_reg};
- assign length_m1 = modulus_length - 8'h1;
+ assign modulus_length_m1 = modulus_length - 8'h1;
+ assign exponent_length_m1 = exponent_length - 8'h1;
//----------------------------------------------------------------
@@ -495,10 +497,10 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
one_new = 32'h00000000;
b_one_new = 32'h00000000;
- if (montprod_opa_addr == length_m1)
+ if (montprod_opa_addr == modulus_length_m1)
one_new = 32'h00000001;
- if (montprod_opb_addr == length_m1)
+ if (montprod_opb_addr == modulus_length_m1)
b_one_new = 32'h00000001;
end
@@ -644,7 +646,7 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
loop_counter_new = 13'b0;
loop_counter_we = 1'b0;
- if (loop_counter_reg == {length_m1, 5'b11111})
+ if (loop_counter_reg == {exponent_length_m1, 5'b11111})
last_iteration = 1'b1;
else
last_iteration = 1'b0;
@@ -678,7 +680,7 @@ module modexp_core #(parameter OPW = 32, parameter ADW = 8)
begin : exponent_process
// Accessing new instead of reg - pick up update at
// CTRL_ITERATE_NEW to remove a pipeline stall.
- E_word_index = length_m1 - loop_counter_new[ 12 : 5 ];
+ E_word_index = exponent_length_m1 - loop_counter_new[ 12 : 5 ];
E_bit_index = loop_counter_reg[ 04 : 0 ];
diff --git a/src/tb/tb_modexp.v b/src/tb/tb_modexp.v
index fe22662..363b4ed 100644
--- a/src/tb/tb_modexp.v
+++ b/src/tb/tb_modexp.v
@@ -256,8 +256,8 @@ module tb_modexp();
dut.core_inst.ready_reg, dut.start_reg, dut.start_new);
$display("residue_valid = 0x%01x", dut.core_inst.residue_valid_reg);
$display("loop_counter_reg = 0x%08x", dut.core_inst.loop_counter_reg);
- $display("exponent_length_reg = 0x%02x, modulus_length_reg = 0x%02x length_m1 = 0x%02x",
- dut.exponent_length_reg, dut.modulus_length_reg, dut.core_inst.length_m1);
+ $display("exponent_length_reg = 0x%02x exponent_length_m1 = 0x%02x modulus_length_reg = 0x%02x modulus_length_m1 = 0x%02x",
+ dut.exponent_length_reg, dut.core_inst.exponent_length_m1, dut.modulus_length_reg, dut.core_inst.modulus_length_m1);
$display("ctrl_reg = 0x%04x", dut.core_inst.modexp_ctrl_reg);
$display("");
end
@@ -885,6 +885,56 @@ module tb_modexp();
//----------------------------------------------------------------
+ // e65537_64bit_modulus_elength()
+ //----------------------------------------------------------------
+ task e65537_64bit_modulus_elength();
+ reg [31 : 0] read_data;
+ begin
+ success = 32'h1;
+ tc_ctr = tc_ctr + 1;
+ $display("Test with e = 65537 and 64 bit modulus, explicit exponent length.");
+
+ write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
+ write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
+
+ write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
+ write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
+ write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f);
+ write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b);
+
+ write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
+ write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
+ write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3);
+ write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b);
+
+ write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
+ write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
+
+ start_test_cycle_ctr();
+
+ // Start processing and wait for ready.
+ write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
+ wait_ready();
+
+ stop_test_cycle_ctr();
+
+ write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
+ read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
+ read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data);
+ read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data);
+
+ if (success !== 1)
+ begin
+ $display("*** ERROR: e65537_64bit_modulus with explicit elength was NOT successful.");
+ error_ctr = error_ctr + 1;
+ end
+ else
+ $display("*** e65537_64bit_modulus success.");
+ end
+ endtask // e65537_64bit_modulus_elength
+
+
+ //----------------------------------------------------------------
// e65537_128bit_modulus()
//----------------------------------------------------------------
task e65537_128bit_modulus();
@@ -1398,10 +1448,11 @@ module tb_modexp();
// tc1();
// tc2();
// tc3();
- autogenerated_BASIC_33bit();
- autogenerated_BASIC_128bit();
+// autogenerated_BASIC_33bit();
+// autogenerated_BASIC_128bit();
e65537_64bit_modulus();
-// e65537_128bit_modulus();
+ e65537_64bit_modulus_elength();
+ // e65537_128bit_modulus();
// e65537_256bit_modulus();
// rob_dec_1024();
diff --git a/src/tb/tb_modexp_autogenerated.v b/src/tb/tb_modexp_autogenerated.v
index 1eb80d5..0bb9432 100644
--- a/src/tb/tb_modexp_autogenerated.v
+++ b/src/tb/tb_modexp_autogenerated.v
@@ -174,8 +174,8 @@ module tb_modexp_autogenerated();
dut.core_inst.ready_reg, dut.start_reg, dut.start_new);
$display("residue_valid = 0x%01x", dut.core_inst.residue_valid_reg);
$display("loop_counter_reg = 0x%08x", dut.core_inst.loop_counter_reg);
- $display("exponent_length_reg = 0x%02x, modulus_length_reg = 0x%02x length_m1 = 0x%02x",
- dut.exponent_length_reg, dut.modulus_length_reg, dut.core_inst.length_m1);
+ $display("exponent_length_reg = 0x%02x, modulus_length_reg = 0x%02x modulus_length_m1 = 0x%02x",
+ dut.exponent_length_reg, dut.modulus_length_reg, dut.core_inst.modulus_length_m1);
$display("ctrl_reg = 0x%04x", dut.core_inst.modexp_ctrl_reg);
$display("");
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-04 11:36:20 +0000