diff options
| -rw-r--r-- | src/rtl/montprod.v | 167 |
1 files changed, 82 insertions, 85 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v index 758fb6d..7c7bf33 100644 --- a/src/rtl/montprod.v +++ b/src/rtl/montprod.v @@ -113,16 +113,17 @@ module montprod( reg [07 : 0] s_mem_wr_addr_reg; wire [31 : 0] s_mem_read_data; - reg q; //q = (s - b * A) & 1 + reg q_new; reg q_reg; - reg b; //b: bit of B + reg b_new; reg b_reg; + reg update_bq; - reg [12 : 0] loop_counter_reg; - reg [12 : 0] loop_counter_new; - reg loop_counter_we; - reg loop_counter_set; - reg loop_counter_dec; + reg [12 : 0] loop_ctr_reg; + reg [12 : 0] loop_ctr_new; + reg loop_ctr_we; + reg loop_ctr_set; + reg loop_ctr_dec; reg [07 : 0] B_word_index; //loop counter as a word index reg [04 : 0] B_bit_index; //loop counter as a bit index @@ -187,14 +188,6 @@ module montprod( ); - adder32 s_adder_sa( - .a(s_mem_read_data), - .b(opa_data), - .carry_in(add_carry_in_sa_reg), - .sum(add_result_sa), - .carry_out(add_carry_out_sa) - ); - adder32 s_adder_sm( .a(s_mem_read_data), .b(opm_data), @@ -203,6 +196,15 @@ module montprod( .carry_out(add_carry_out_sm) ); + + adder32 s_adder_sa( + .a(s_mem_read_data), + .b(opa_data), + .carry_in(add_carry_in_sa_reg), + .sum(add_result_sa), + .carry_out(add_carry_out_sa) + ); + shr32 shifter( .a(s_mem_read_data), .carry_in(shr_carry_in_reg), @@ -223,7 +225,7 @@ module montprod( if (!reset_n) begin ready_reg <= 1'b0; - loop_counter_reg <= 13'h0; + loop_ctr_reg <= 13'h0; word_index_reg <= 8'h0; word_index_prev_reg <= 8'h0; add_carry_in_sa_reg <= 1'b0; @@ -251,16 +253,18 @@ module montprod( B_bit_index_reg <= B_bit_index; - q_reg <= q; - b_reg <= b; - + if (update_bq) + begin + b_reg <= b_new; + q_reg <= q_new; + end s_mux_reg <= s_mux_new; if (ready_we) ready_reg <= ready_new; - if (loop_counter_we) - loop_counter_reg <= loop_counter_new; + if (loop_ctr_we) + loop_ctr_reg <= loop_ctr_new; if (montprod_ctrl_we) begin @@ -271,60 +275,6 @@ module montprod( //---------------------------------------------------------------- - // bq - //---------------------------------------------------------------- - always @* - begin : bq - b = b_reg; - q = q_reg; - - if (montprod_ctrl_reg == CTRL_LOOP_BQ) - begin - b = opb_data[ B_bit_index_reg ]; - //opa_addr will point to length-1 to get A LSB. - //s_read_addr will point to length-1 - q = s_mem_read_data[0] ^ (opa_data[0] & b); - - if (DEBUG) - $display("s_mem_read_data: %x opa_data %x b %x q %x B_bit_index_reg %x", - s_mem_read_data, opa_data, b, q, B_bit_index_reg); - end - end // bq - - - //---------------------------------------------------------------- - // loop_counter_process - // Process for iterating the loop counter and setting - // related B indices. - //---------------------------------------------------------------- - always @* - begin : loop_counter_process - loop_counter_new = loop_counter_reg; - loop_counter_we = 1'b0; - length_m1 = length - 1'b1; - B_bit_index = B_bit_index_reg; - B_word_index = loop_counter_reg[12:5]; - - if (loop_counter_set) - begin - loop_counter_new = {length, 5'b00000} - 1'b1; - loop_counter_we = 1'b1; - end - - if (loop_counter_dec) - begin - loop_counter_new = loop_counter_reg - 1'b1; - loop_counter_we = 1'b1; - end - - if (set_B_bit_index) - begin - B_bit_index = 5'h1f - loop_counter_reg[4:0]; - end - end - - - //---------------------------------------------------------------- // prodcalc //---------------------------------------------------------------- always @* @@ -449,24 +399,70 @@ module montprod( //---------------------------------------------------------------- + // bq + // b: bit of B + // q = (s - b * A) & 1 + //---------------------------------------------------------------- + always @* + begin : bq + b_new = opb_data[B_bit_index_reg]; + q_new = s_mem_read_data[0] ^ (opa_data[0] & b_new); + end // bq + + + //---------------------------------------------------------------- + // loop_ctr + // Logic for updating the loop counter and + // setting related B indices. + //---------------------------------------------------------------- + always @* + begin : loop_ctr + loop_ctr_new = loop_ctr_reg; + loop_ctr_we = 1'b0; + length_m1 = length - 1'b1; + B_bit_index = B_bit_index_reg; + B_word_index = loop_ctr_reg[12:5]; + + if (loop_ctr_set) + begin + loop_ctr_new = {length, 5'b00000} - 1'b1; + loop_ctr_we = 1'b1; + end + + if (loop_ctr_dec) + begin + loop_ctr_new = loop_ctr_reg - 1'b1; + loop_ctr_we = 1'b1; + end + + if (set_B_bit_index) + begin + B_bit_index = 5'h1f - loop_ctr_reg[4:0]; + end + end + + + //---------------------------------------------------------------- // montprod_ctrl // // Control FSM for the montgomery product calculator. //---------------------------------------------------------------- always @* begin : montprod_ctrl - ready_new = 1'b0; - ready_we = 1'b0; - montprod_ctrl_new = CTRL_IDLE; - montprod_ctrl_we = 1'b0; + ready_new = 1'b0; + ready_we = 1'b0; + montprod_ctrl_new = CTRL_IDLE; + montprod_ctrl_we = 1'b0; - loop_counter_set = 1'b0; - loop_counter_dec = 1'b0; - set_B_bit_index = 1'b0; + loop_ctr_set = 1'b0; + loop_ctr_dec = 1'b0; + set_B_bit_index = 1'b0; + update_bq = 1'b0; reset_word_index_LSW = 1'b0; reset_word_index_MSW = 1'b0; + case (montprod_ctrl_reg) CTRL_IDLE: begin @@ -489,7 +485,7 @@ module montprod( begin if (word_index_reg == 8'h0) begin - loop_counter_set = 1'b1; + loop_ctr_set = 1'b1; montprod_ctrl_new = CTRL_WAIT; montprod_ctrl_we = 1'b1; end @@ -514,6 +510,7 @@ module montprod( CTRL_LOOP_BQ: begin reset_word_index_LSW = 1'b1; + update_bq = 1'b1; montprod_ctrl_new = CTRL_L_CALC_SM; montprod_ctrl_we = 1'b1; end @@ -563,12 +560,12 @@ module montprod( CTRL_L_STALLPIPE_D2: begin - loop_counter_dec = 1'b1; + loop_ctr_dec = 1'b1; montprod_ctrl_new = CTRL_LOOP_ITER; montprod_ctrl_we = 1'b1; reset_word_index_LSW = 1'b1; - if (loop_counter_reg == 0) + if (loop_ctr_reg == 0) begin montprod_ctrl_new = CTRL_L_STALLPIPE_ES; montprod_ctrl_we = 1'b1; |