diff options
| -rw-r--r-- | src/rtl/montprod.v | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v index a0ca302..279f5aa 100644 --- a/src/rtl/montprod.v +++ b/src/rtl/montprod.v @@ -100,7 +100,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) reg s_mem_we_new; reg [(ADW - 1) : 0] s_mem_read_addr_reg; - reg [(ADW - 1) : 0] s_mem_write_addr_reg; reg q_new; reg q_reg; @@ -161,6 +160,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) wire [(OPW - 1) : 0] s_mem_read_data; reg [(ADW - 1) : 0] s_mem_write_addr; reg [(OPW - 1) : 0] s_mem_write_data; + reg [(OPW - 1) : 0] tmp_s_mem_write_data; reg [(OPW - 1) : 0] sa_adder_data_in; reg [(OPW - 1) : 0] muxed_s_mem_read_data; @@ -168,9 +168,9 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) wire [(ADW - 1) : 0] length_m1; // Temporary debug wires. - reg b_js; - reg pr_tt; - reg s_mem_we; + reg [1 : 0] state_trace; + reg [1 : 0] mux_trace; + reg s_mem_we; //---------------------------------------------------------------- @@ -312,6 +312,9 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) s_mem_write_data = {OPW{1'b0}}; s_mem_we_new = 1'b0; s_mem_we = 1'b0; + state_trace = 0; + mux_trace = 0; + tmp_s_mem_write_data = {OPW{1'b0}}; case (montprod_ctrl_reg) CTRL_LOOP_ITER: @@ -323,6 +326,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) begin //s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles. s_mem_we_new = b_reg | q_reg | first_iteration_reg; + state_trace = 1; end CTRL_CALC_SDIV2: @@ -340,6 +344,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) case (s_mux_reg) SMUX_ADD: begin + mux_trace = 1; s_mem_we = b_reg | q_reg | first_iteration_reg; if (first_iteration_reg) @@ -354,14 +359,15 @@ module montprod #(parameter OPW = 32, parameter ADW = 8) sa_adder_data_in = muxed_s_mem_read_data; if (b_reg) - s_mem_write_data = add_result_sa; + tmp_s_mem_write_data = add_result_sa; else if (q_reg) - s_mem_write_data = add_result_sm; + tmp_s_mem_write_data = add_result_sm; else if (first_iteration_reg) - s_mem_write_data = {OPW{1'b0}}; + tmp_s_mem_write_data = {OPW{1'b0}}; else - s_mem_write_data = s_mem_read_data; + tmp_s_mem_write_data = s_mem_read_data; + s_mem_write_data = tmp_s_mem_write_data; add_carry_in_sa_new = add_carry_out_sa; add_carry_in_sm_new = add_carry_out_sm; end |