diff options
| -rw-r--r-- | src/rtl/modexp.v | 140 | ||||
| -rw-r--r-- | src/rtl/shl32.v | 28 | ||||
| -rw-r--r-- | src/rtl/shr32.v | 26 |
3 files changed, 128 insertions, 66 deletions
diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v index 8721ce9..dbf65b3 100644 --- a/src/rtl/modexp.v +++ b/src/rtl/modexp.v @@ -17,7 +17,7 @@ // // The core has a 32-bit memory like interface, but provides // status signals to inform the system that a given operation -// has completed. Additionally, any errors will also be asserted. +// has is done. Additionally, any errors will also be asserted. // // // Author: Joachim Strombergson, Peter Magnusson @@ -71,8 +71,8 @@ module modexp( localparam ADDR_NAME0 = 8'h00; localparam ADDR_NAME1 = 8'h01; localparam ADDR_VERSION = 8'h02; + localparam ADDR_CTRL = 8'h03; - localparam ADDR_CTRL = 8'h00; localparam CTRL_INIT_BIT = 0; localparam CTRL_NEXT_BIT = 1; @@ -154,17 +154,6 @@ module modexp( reg [31 : 0] result_mem_int_wr_data; reg result_mem_int_we; - reg residue_calculator_start; //TODO not implemented yet - reg residue_calculator_ready; //TODO not implemented yet - - reg [31 : 0] residue_mem [0 : 255]; - reg [07 : 0] residue_mem_rd_addr; - wire [31 : 0] residue_mem_rd_data; - reg [07 : 0] residue_mem_wr_addr; - reg [31 : 0] residue_mem_wr_data; - reg residue_mem_we; - - reg [07 : 0] p_mem_rd0_addr; wire [31 : 0] p_mem_rd0_data; reg [07 : 0] p_mem_rd1_addr; @@ -175,13 +164,13 @@ module modexp( reg [07 : 0] length_reg; reg [07 : 0] length_m1_reg; - reg [07 : 0] length_new; - reg [07 : 0] length_m1_new; - reg length_we; + reg [07 : 0] length_new; //TODO: API should write length!!! + reg [07 : 0] length_m1_new; //TODO: API should write length-1 when writing length!!! + reg length_we; //TODO: API should enable length_we!!! reg start_reg; - reg start_new; - reg start_we; + reg start_new; //TODO: API should start operations!!! + reg start_we; //TODO: API should start operations!!! reg ready_reg; reg ready_new; @@ -192,7 +181,7 @@ module modexp( reg montprod_select_we; reg [1 : 0] montprod_dest_reg; reg [1 : 0] montprod_dest_new; - reg [1 : 0] montprod_dest_we; + reg montprod_dest_we; reg [3 : 0] modexp_ctrl_reg; reg [3 : 0] modexp_ctrl_new; @@ -203,7 +192,7 @@ module modexp( reg [12 : 0] loop_counter_reg; reg [12 : 0] loop_counter_new; - reg [12 : 0] loop_counter_we; + reg loop_counter_we; reg [07 : 0] E_word_index; reg [04 : 0] E_bit_index; reg last_iteration; @@ -215,7 +204,7 @@ module modexp( // Wires. //---------------------------------------------------------------- reg [31 : 0] tmp_read_data; - reg tmp_error; + //reg tmp_error; reg montprod_calc; wire montprod_ready; @@ -234,6 +223,21 @@ module modexp( wire [31 : 0] montprod_result_data; wire montprod_result_we; + reg residue_calculate; + wire residue_ready; + //wire residue_wire; ? + reg [14 : 0] residue_nn; + wire [07 : 0] residue_length; + wire [07 : 0] residue_opa_rd_addr; + reg [31 : 0] residue_opa_rd_data; + wire [07 : 0] residue_opa_wr_addr; + wire [31 : 0] residue_opa_wr_data; + wire residue_opa_wr_we; + wire [07 : 0] residue_opm_addr; + reg [31 : 0] residue_opm_data; + + reg [07 : 0] residue_mem_montprod_read_addr; + wire [31 : 0] residue_mem_montprod_read_data; //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -260,7 +264,7 @@ module modexp( .opb_data(montprod_opb_data), .opm_addr(montprod_opm_addr), - .opm_data(message_mem_int_rd_data), + .opm_data(montprod_opm_data), .result_addr(montprod_result_addr), .result_data(montprod_result_data), @@ -268,6 +272,33 @@ module modexp( ); + residue residue_inst( + .clk(clk), + .reset_n(reset_n), + .calculate(residue_calculate), + .ready(residue_ready), + .nn(residue_nn), + .length(residue_length), + .opa_rd_addr(residue_opa_rd_addr), + .opa_rd_data(residue_opa_rd_data), + .opa_wr_addr(residue_opa_wr_addr), + .opa_wr_data(residue_opa_wr_data), + .opa_wr_we(residue_opa_wr_we), + .opm_addr(residue_opm_addr), + .opm_data(residue_opm_data) + ); + + blockmem2r1w residue_mem( + .clk(clk), + .read_addr0(residue_opa_rd_addr), + .read_data0(residue_opa_rd_data), + .read_addr1(residue_mem_montprod_read_addr), + .read_data1(residue_mem_montprod_read_data), + .wr(residue_opa_wr_we), + .write_addr(residue_opa_wr_addr), + .write_data(residue_opa_wr_data) + ); + blockmem2r1w modulus_mem( .clk(clk), .read_addr0(modulus_mem_int_rd_addr), @@ -487,6 +518,40 @@ module modexp( //---------------------------------------------------------------- + // one + // + // generates the big integer one ( 00... 01 ) + //---------------------------------------------------------------- + always @* + begin : one_process; + if (montprod_opa_addr == length_m1_reg) + one_new = 32'h00000001; + else + one_new = 32'h00000000; + end + + //---------------------------------------------------------------- + // read mux for modulus, since it is being addressed by two sources + //---------------------------------------------------------------- + always @* + begin : modulus_mem_reader_process + if (modexp_ctrl_reg == CTRL_RESIDUE) + modulus_mem_int_rd_addr = residue_opm_addr; + else + modulus_mem_int_rd_addr = montprod_opm_addr; + end + + //---------------------------------------------------------------- + // feeds residue calculator + //---------------------------------------------------------------- + always @* + begin : residue_process; + residue_nn = { 1'b0, length_reg, 6'h0 }; //N*2, N=length*32, *32 = shl5, *64 = shl6 + residue_length = length_reg; + residue_opm_data = modulus_mem_int_rd_data; + end + + //---------------------------------------------------------------- // montprod_op_select // // Select operands used during montprod calculations depending @@ -494,33 +559,28 @@ module modexp( //---------------------------------------------------------------- always @* begin : montprod_op_select - message_mem_int_rd_addr = montprod_opa_addr; - p_mem_rd0_addr = montprod_opa_addr; - - residue_mem_rd_addr = montprod_opb_addr; - p_mem_rd1_addr = montprod_opb_addr; - modulus_mem_int_rd_addr = montprod_opm_addr; + montprod_length = length_reg; - montprod_opa_data = 32'h00000000; - montprod_opb_data = 32'h00000000; + result_mem_int_rd_addr = montprod_opa_addr; + message_mem_int_rd_addr = montprod_opa_addr; + p_mem_rd0_addr = montprod_opa_addr; - if (montprod_opa_addr == length_m1_reg) - one_new = 32'h00000001; - else - one_new = 32'h00000000; + residue_mem_montprod_read_addr = montprod_opb_addr; + p_mem_rd1_addr = montprod_opb_addr; + montprod_opm_data = modulus_mem_int_rd_data; case (montprod_select_reg) MONTPROD_SELECT_ONE_NR: begin montprod_opa_data = one; - montprod_opb_data = residue_mem_rd_data; + montprod_opb_data = residue_mem_montprod_read_data; end MONTPROD_SELECT_X_NR: begin montprod_opa_data = message_mem_int_rd_data; - montprod_opb_data = residue_mem_rd_data; + montprod_opb_data = residue_mem_montprod_read_data; end MONTPROD_SELECT_Z_P: @@ -543,6 +603,8 @@ module modexp( default: begin + montprod_opa_data = 32'h00000000; + montprod_opb_data = 32'h00000000; end endcase // case (montprod_selcect_reg) end @@ -654,7 +716,7 @@ module modexp( modexp_ctrl_new = CTRL_IDLE; modexp_ctrl_we = 0; - residue_calculator_start = 1'b0; + residue_calculate = 1'b0; case (modexp_ctrl_reg) CTRL_IDLE: @@ -665,13 +727,13 @@ module modexp( begin modexp_ctrl_new = CTRL_RESIDUE; modexp_ctrl_we = 1; - residue_calculator_start = 1'b1; + residue_calculate = 1'b1; end end CTRL_RESIDUE: begin - if (residue_calculator_ready == 1'b1) + if (residue_ready == 1'b1) begin montprod_select_new = MONTPROD_SELECT_ONE_NR; montprod_select_we = 1; diff --git a/src/rtl/shl32.v b/src/rtl/shl32.v index d0dd1bc..42521fd 100644 --- a/src/rtl/shl32.v +++ b/src/rtl/shl32.v @@ -1,8 +1,8 @@ //====================================================================== // -// shr32.v -// --------- -// 32bit shifter with carry in / carry out. +// shl32.v +// ------- +// 32bit left shift with carry in / carry out // // // Author: Peter Magnusson @@ -36,18 +36,18 @@ // //====================================================================== - module shl32( - input [31 : 0] a, - input carry_in, - output wire [31 : 0] amul2, - output wire carry_out); + input wire [31 : 0] a, + input wire carry_in, + output wire [31 : 0] amul2, + output wire carry_out + ); - reg [32 : 0] shl_result; + assign amul2 = {a[30 : 0], carry_in}; + assign carry_out = a[31]; - assign amul2 = shl_result[31:0]; - assign carry_out = shl_result[32]; +endmodule // shl32 - always @(a, carry_in) - shl_result = { a, carry_in }; -endmodule +//====================================================================== +// EOF shl32.v +//====================================================================== diff --git a/src/rtl/shr32.v b/src/rtl/shr32.v index 840f9df..66b15c3 100644 --- a/src/rtl/shr32.v +++ b/src/rtl/shr32.v @@ -1,8 +1,8 @@ //====================================================================== // // shr32.v -// --------- -// 32bit shifter with carry in / carry out +// ------- +// 32bit right shift with carry in / carry out. // // // Author: Peter Magnusson @@ -36,18 +36,18 @@ // //====================================================================== - module shr32( - input [31 : 0] a, - input carry_in, - output wire [31 : 0] adiv2, - output wire carry_out); + input wire [31 : 0] a, + input wire carry_in, + output wire [31 : 0] adiv2, + output wire carry_out + ); - reg [32 : 0] shr_result; + assign adiv2 = {carry_in, a[31 : 1]}; + assign carry_out = a[0]; - assign adiv2 = shr_result[32:1]; - assign carry_out = shr_result[0]; +endmodule // shr32 - always @(a, carry_in) - shr_result = { carry_in, a }; -endmodule +//====================================================================== +// EOF shr32.v +//====================================================================== |