diff options
| -rw-r--r-- | src/tb/tb_montprod.v | 142 |
1 files changed, 73 insertions, 69 deletions
diff --git a/src/tb/tb_montprod.v b/src/tb/tb_montprod.v index e581e36..2cadd78 100644 --- a/src/tb/tb_montprod.v +++ b/src/tb/tb_montprod.v @@ -50,14 +50,15 @@ module tb_montprod(); parameter CLK_HALF_PERIOD = 2; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; - parameter SHOW_INIT = 0; - parameter DUMP_MEM = 0; - parameter DEBUG = 0; - parameter SHOW_WRITE_MEM = 0; - parameter SHOW_S_MONITOR = 0; - parameter SHOW_BQ_DEBUG = 0; - parameter SHOW_FSM_STATUS = 0; - parameter DISPLAY_TEST_CYCLES = 1; + parameter SHOW_INIT = 0; + parameter DUMP_MEM = 0; + parameter DEBUG = 0; + parameter SHOW_WRITE_MEM = 0; + parameter SHOW_WRITE_RESULT_MEM = 0; + parameter SHOW_S_MONITOR = 0; + parameter SHOW_BQ_DEBUG = 0; + parameter SHOW_FSM_STATUS = 0; + parameter DISPLAY_TEST_CYCLES = 1; parameter WAIT_TIMEOUT = 100000000; @@ -65,10 +66,6 @@ module tb_montprod(); //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- - reg [31 : 0] test_cycle_ctr; - reg test_cycle_ctr_rst; - reg test_cycle_ctr_inc; - reg tb_clk; reg tb_reset_n; reg tb_calculate; @@ -84,6 +81,10 @@ module tb_montprod(); wire [31 : 0] tb_result_data; wire tb_result_we; + reg [31 : 0] test_cycle_ctr; + reg test_cycle_ctr_rst; + reg test_cycle_ctr_inc; + reg [31 : 0] tb_a [0 : 255]; //tb_opa_data reg [31 : 0] tb_b [0 : 255]; //tb_opb_data reads here reg [31 : 0] tb_m [0 : 255]; //tb_opm_data reads here @@ -92,6 +93,7 @@ module tb_montprod(); integer test_mont_prod_success; integer test_mont_prod_fail; + //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- @@ -113,10 +115,8 @@ module tb_montprod(); ); - //---------------------------------------------------------------- // clk_gen - // // Clock generator process. //---------------------------------------------------------------- always @@ -175,70 +175,36 @@ module tb_montprod(); //---------------------------------------------------------------- - // reset_dut() - // - // Toggles reset to force the DUT into a well defined state. - //---------------------------------------------------------------- - task reset_dut(); - begin - $display("*** Toggle reset."); - tb_reset_n = 0; - #(2 * CLK_PERIOD); - tb_reset_n = 1; - end - endtask // reset_dut - - - //---------------------------------------------------------------- - // init_sim() - // - // Initialize all counters and testbed functionality as well - // as setting the DUT inputs to defined values. - //---------------------------------------------------------------- - task init_sim(); - begin - $display("*** init_sim"); - tb_clk = 0; - tb_reset_n = 0; - tb_length = 0; - tb_calculate = 0; - test_mont_prod_success = 0; - test_mont_prod_fail = 0; - end - endtask // init_sim - - - //---------------------------------------------------------------- - // dump_test_memory + // read_test_memory //---------------------------------------------------------------- always @(posedge tb_clk) - begin : dump_test_memory + begin : read_test_memory tb_opa_data <= tb_a[tb_opa_addr]; tb_opb_data <= tb_b[tb_opb_addr]; tb_opm_data <= tb_m[tb_opm_addr]; if (DUMP_MEM) - $display("a %x %x b %x %x m %x %x", tb_opa_addr, tb_a[tb_opa_addr], - tb_opb_addr, tb_b[tb_opb_addr], tb_opm_addr, tb_m[tb_opm_addr]); + $display("a %x %x b %x %x m %x %x", tb_opa_addr, tb_a[tb_opa_addr], tb_opb_addr, tb_b[tb_opb_addr], tb_opm_addr, tb_m[tb_opm_addr]); end //---------------------------------------------------------------- - // write_test_memory + // write_result_memory //---------------------------------------------------------------- always @* - begin : write_test_memory - if (SHOW_WRITE_MEM) - if (tb_result_we == 1'b1) - begin - $display("write %d: %x", tb_result_addr, tb_result_data); - tb_r[tb_result_addr] = tb_result_data; - end - end + begin : write_result_memory + if (tb_result_we == 1'b1) + begin + tb_r[tb_result_addr] = tb_result_data; + + if (SHOW_WRITE_RESULT_MEM) + $display("write result mnen 0x%02%x: 0x%08x", tb_result_addr, tb_result_data); + end + end //---------------------------------------------------------------- - // S monitor + // s_monitor //---------------------------------------------------------------- always @ (posedge tb_clk) begin : s_monitor @@ -258,18 +224,18 @@ module tb_montprod(); always @ (posedge tb_clk) begin : bq_debug if (SHOW_BQ_DEBUG) - if (dut.montprod_ctrl_reg == dut.CTRL_L_CALC_SM) - $display("====================> B: %x Q: %x B_bit_index_reg: %x <=====================", - dut.b_reg, dut.q_reg, dut.B_bit_index_reg); + begin + if (dut.montprod_ctrl_reg == dut.CTRL_L_CALC_SM) + $display("====================> B: %x Q: %x B_bit_index_reg: %x <=====================", dut.b_reg, dut.q_reg, dut.B_bit_index_reg); + end end //---------------------------------------------------------------- - // fmsm_debug - // Display control FSM status. + // fsm_monitor //---------------------------------------------------------------- always @ (posedge tb_clk) - begin : fsm_debug + begin : fsm_monitor if (SHOW_FSM_STATUS) if (dut.montprod_ctrl_we) case (dut.montprod_ctrl_new) @@ -302,6 +268,40 @@ module tb_montprod(); //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut(); + begin + $display("*** Toggle reset."); + tb_reset_n = 0; + #(2 * CLK_PERIOD); + tb_reset_n = 1; + end + endtask // reset_dut + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim(); + begin + $display("*** init_sim"); + tb_clk = 0; + tb_reset_n = 0; + tb_length = 0; + tb_calculate = 0; + test_mont_prod_success = 0; + test_mont_prod_fail = 0; + end + endtask // init_sim + + + //---------------------------------------------------------------- // wait_ready() // // Wait for the ready flag in the dut to be set. @@ -333,6 +333,10 @@ module tb_montprod(); //---------------------------------------------------------------- + // signal_calculate() + // + // Start the montgomery calculation by pulling the calculate + // flag to the dut. //---------------------------------------------------------------- task signal_calculate(); begin @@ -495,7 +499,7 @@ module tb_montprod(); reset_dut(); short_tests(); - long_tests(); +// long_tests(); $display(" -- Testbench for montprod done. --"); $display(" tests success: %d", test_mont_prod_success); |