diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-18 12:44:46 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-18 12:44:46 +0200 |
commit | 1e676b4c463e6a5e75a4d81578b139a51059a601 (patch) | |
tree | fa56dade05b7ed5607c681989db15f47215abb85 /src | |
parent | 90337c66cc1a644b27a4ed8e188b1aa4e07fea67 (diff) |
Adding iteration flag to be used to remove zero fill of s_mem.
Diffstat (limited to 'src')
-rw-r--r-- | src/rtl/montprod.v | 55 |
1 files changed, 30 insertions, 25 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v index 465bd70..cd7d5a9 100644 --- a/src/rtl/montprod.v +++ b/src/rtl/montprod.v @@ -142,10 +142,9 @@ module montprod( reg shr_carry_in_reg; reg shr_carry_in_new; - reg reset_word_index_lsw; - reg reset_word_index_msw; - - reg [31 : 0] sa_adder_data_in; + reg first_iteration_reg; + reg first_iteration_new; + reg first_iteration_we; //---------------------------------------------------------------- @@ -161,6 +160,11 @@ module montprod( wire shr_carry_out; wire [31 : 0] shr_data_out; + reg reset_word_index_lsw; + reg reset_word_index_msw; + + reg [31 : 0] sa_adder_data_in; + //---------------------------------------------------------------- @@ -226,7 +230,7 @@ module montprod( begin : reg_update if (!reset_n) begin - ready_reg <= 1'b0; + ready_reg <= 1'b1; loop_ctr_reg <= 13'h0; word_index_reg <= 8'h0; word_index_prev_reg <= 8'h0; @@ -239,6 +243,7 @@ module montprod( s_mem_we_reg <= 1'b0; s_mem_wr_addr_reg <= 8'h0; b_bit_index_reg <= 5'h0; + first_iteration_reg <= 1'b0; montprod_ctrl_reg <= CTRL_IDLE; end else @@ -254,6 +259,9 @@ module montprod( add_carry_in_sa_reg <= add_carry_in_sa_new; add_carry_in_sm_reg <= add_carry_in_sm_new; + if (first_iteration_we) + first_iteration_reg <= first_iteration_new; + if (b_bit_index_we) b_bit_index_reg <= b_bit_index_new; @@ -445,21 +453,19 @@ module montprod( //---------------------------------------------------------------- always @* begin : montprod_ctrl - ready_new = 1'b0; - ready_we = 1'b0; - montprod_ctrl_new = CTRL_IDLE; - montprod_ctrl_we = 1'b0; - - loop_ctr_set = 1'b0; - loop_ctr_dec = 1'b0; - b_bit_index_we = 1'b0; - bq_we = 1'b0; - - s_mux_new = SMUX_0; - + ready_new = 1'b0; + ready_we = 1'b0; + loop_ctr_set = 1'b0; + loop_ctr_dec = 1'b0; + b_bit_index_we = 1'b0; + bq_we = 1'b0; + s_mux_new = SMUX_0; reset_word_index_lsw = 1'b0; reset_word_index_msw = 1'b0; - + first_iteration_new = 1'b0; + first_iteration_we = 1'b0; + montprod_ctrl_new = CTRL_IDLE; + montprod_ctrl_we = 1'b0; case (montprod_ctrl_reg) CTRL_IDLE: @@ -468,14 +474,11 @@ module montprod( begin ready_new = 1'b0; ready_we = 1'b1; - montprod_ctrl_new = CTRL_INIT_S; - montprod_ctrl_we = 1'b1; reset_word_index_lsw = 1'b1; - end - else - begin - ready_new = 1'b1; - ready_we = 1'b1; + first_iteration_new = 1'b1; + first_iteration_we = 1'b1; + montprod_ctrl_new = CTRL_INIT_S; + montprod_ctrl_we = 1'b1; end end @@ -529,6 +532,8 @@ module montprod( CTRL_L_STALLPIPE_SA: begin + first_iteration_new = 1'b0; + first_iteration_we = 1'b1; montprod_ctrl_new = CTRL_L_CALC_SDIV2; montprod_ctrl_we = 1'b1; reset_word_index_msw = 1'b1; |