Updating modexp core to v 0.50. This version contains a working core that can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.

1 files changed, 53 insertions, 1 deletions

diff --git a/src/tb/tb_modexp_autogenerated_template.v b/src/tb/tb_modexp_autogenerated_template.v
index 62ab7dc..eea4e7f 100644
--- a/src/tb/tb_modexp_autogenerated_template.v
+++ b/src/tb/tb_modexp_autogenerated_template.v
@@ -50,7 +50,7 @@ module tb_modexp_autogenerated();
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  parameter DEBUG = 1;
+  parameter DEBUG = 0;
 
   localparam CLK_HALF_PERIOD = 1;
   localparam CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
@@ -445,8 +445,60 @@ module tb_modexp_autogenerated();
     end
   endtask // dump_memories
 
+  function assertEquals(
+      input [31:0] expected,
+      input [31:0] actual
+    );
+    begin
+      if (expected === actual)
+        begin
+          assertEquals = 1; // success
+        end
+      else
+        begin
+          $display("Expected: 0x%08x, got 0x%08x", expected, actual);
+          assertEquals = 0; // failure
+        end
+    end
+  endfunction // assertEquals
+
+  integer success;
+
 // ===TEMPLATE_HEADER_END===
 
+  task TEMPLATE_TASK_NAME();
+    reg [31 : 0] read_data;
+    begin
+      success = 32'h1;
+      tc_ctr = tc_ctr + 1;
+      $display("TEMPLATE_TASK_NAME");
+
+      write_word({MESSAGE_PREFIX, 8'h#TI#}, 32'h#TD#); //TEMPLATE_MESSAGE_VALES
+      write_word({EXPONENT_PREFIX, 8'h#TI#}, 32'h#TD#); //TEMPLATE_EXPONENT_VALES
+      write_word({MODULUS_PREFIX, 8'h#TI#}, 32'h#TD#); //TEMPLATE_MODULUS_VALUES
+
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h#TL#); //TEMPLATE_MESSAGE_LENGTH
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h#TL#); //TEMPLATE_MODULUS_LENGTH
+
+      // Start processing and wait for ready.
+      write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
+      wait_ready();
+
+      read_word({RESULT_PREFIX, 8'h#TI#}); read_data = tb_read_data; success = success & assertEquals(32'h#TD#, read_data); //TEMPLATE_EXPECTED_VALUES 
+     
+      if (success !== 1)
+        begin  
+          $display("*** ERROR: TEMPLATE_TASK_NAME was NOT successful.");
+          error_ctr = error_ctr + 1;
+        end
+      else
+        $display("*** TEMPLATE_TASK_NAME success.");
+    end
+  endtask // TEMPLATE_TASK_NAME
+
+
+// ===TEMPLATE_TEST_DEFINITION_END===
+
   //----------------------------------------------------------------
   // main
   //