diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-30 16:44:06 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-30 16:44:06 +0200 |
commit | e61c65059054df407206e58b88a1b203f5ad3c3e (patch) | |
tree | d2532e49595096dfaa38528a07f24f70d11a7d4f /src/rtl | |
parent | 4e43d0acb92dd3110b89e9b153b9c0ecb441c655 (diff) |
Fixed missing parenthesis in block memories that reduced mem sizes. Added test cases that verifies that we can work with 2048 bit operands.
Diffstat (limited to 'src/rtl')
-rw-r--r-- | src/rtl/blockmem2r1w.v | 2 | ||||
-rw-r--r-- | src/rtl/blockmem2r1wptr.v | 2 | ||||
-rw-r--r-- | src/rtl/blockmem2rptr1w.v | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/rtl/blockmem2r1w.v b/src/rtl/blockmem2r1w.v index 557e810..aa44101 100644 --- a/src/rtl/blockmem2r1w.v +++ b/src/rtl/blockmem2r1w.v @@ -54,7 +54,7 @@ module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8) input wire [(OPW - 1) : 0] write_data ); - reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)]; + reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)]; reg [(OPW - 1) : 0] tmp_read_data0; reg [(OPW - 1) : 0] tmp_read_data1; diff --git a/src/rtl/blockmem2r1wptr.v b/src/rtl/blockmem2r1wptr.v index b9abfa8..2435cfd 100644 --- a/src/rtl/blockmem2r1wptr.v +++ b/src/rtl/blockmem2r1wptr.v @@ -67,7 +67,7 @@ module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8) //---------------------------------------------------------------- // Memories and regs including update variables and write enable. //---------------------------------------------------------------- - reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)]; + reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)]; reg [(OPW - 1) : 0] tmp_read_data0; reg [31 : 0] tmp_read_data1; diff --git a/src/rtl/blockmem2rptr1w.v b/src/rtl/blockmem2rptr1w.v index fc7d83a..a1d7448 100644 --- a/src/rtl/blockmem2rptr1w.v +++ b/src/rtl/blockmem2rptr1w.v @@ -65,7 +65,7 @@ module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8) //---------------------------------------------------------------- // Memories and regs including update variables and write enable. //---------------------------------------------------------------- - reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)]; + reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)]; reg [(OPW - 1) : 0] tmp_read_data0; reg [31 : 0] tmp_read_data1; |