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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-05-19 13:56:11 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-05-19 13:56:11 +0200
commitedd192a721f3a5e00fd264c12546301ec1f25571 (patch)
tree368fcbacb3ef25d334d8637afd784b274b83e21b /src/rtl
parent24ef45bd82e0dd87ac913634d9f339f612663638 (diff)
Updated TB to use access ports. Added missing invalidate of residue when modulus is updated. Minor cleanup.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/modexp.v329
1 files changed, 187 insertions, 142 deletions
diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v
index afd7a84..30b703e 100644
--- a/src/rtl/modexp.v
+++ b/src/rtl/modexp.v
@@ -24,33 +24,34 @@
//
//
// Author: Joachim Strombergson, Peter Magnusson
-// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, Assured AB
+// All rights reserved.
//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -86,27 +87,19 @@ module modexp(
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_LENGTH = 8'h22; // Should be deprecated.
+ localparam ADDR_MODULUS_PTR_RST = 8'h30;
+ localparam ADDR_MODULUS_DATA = 8'h31;
- localparam MODULUS_PREFIX = 4'h1;
- localparam ADDR_MODULUS_START = 8'h00;
- localparam ADDR_MODULUS_END = 8'hff;
-
-
- localparam EXPONENT_PREFIX = 4'h2;
- localparam ADDR_EXPONENT_START = 8'h00;
- localparam ADDR_EXPONENT_END = 8'hff;
+ localparam ADDR_EXPONENT_PTR_RST = 8'h40;
+ localparam ADDR_EXPONENT_DATA = 8'h41;
+ localparam ADDR_MESSAGE_PTR_RST = 8'h50;
+ localparam ADDR_MESSAGE_DATA = 8'h51;
- localparam MESSAGE_PREFIX = 4'h3;
- localparam MESSAGE_START = 8'h00;
- localparam MESSAGE_END = 8'hff;
+ localparam ADDR_RESULT_PTR_RST = 8'h60;
+ localparam ADDR_RESULT_DATA = 8'h61;
-
- localparam RESULT_PREFIX = 4'h4;
- localparam RESULT_START = 8'h00;
- localparam RESULT_END = 8'hff;
-
- localparam DEFAULT_MODLENGTH = 8'h80;
+ localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam MONTPROD_SELECT_ONE_NR = 3'h0;
@@ -136,7 +129,7 @@ module modexp(
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
- localparam CORE_VERSION = 32'h302e3530; // "0.50"
+ localparam CORE_VERSION = 32'h302e3531; // "0.51"
//----------------------------------------------------------------
@@ -204,17 +197,14 @@ module modexp(
reg [07 : 0] modulus_mem_int_rd_addr;
wire [31 : 0] modulus_mem_int_rd_data;
wire [31 : 0] modulus_mem_api_rd_data;
- reg modulus_mem_api_we;
reg [07 : 0] message_mem_int_rd_addr;
wire [31 : 0] message_mem_int_rd_data;
wire [31 : 0] message_mem_api_rd_data;
- reg message_mem_api_we;
reg [07 : 0] exponent_mem_int_rd_addr;
wire [31 : 0] exponent_mem_int_rd_data;
wire [31 : 0] exponent_mem_api_rd_data;
- reg exponent_mem_api_we;
wire [31 : 0] result_mem_api_rd_data;
reg [07 : 0] result_mem_int_rd_addr;
@@ -271,6 +261,22 @@ module modexp(
reg invalidate_residue;
reg residue_valid_int_validated;
+ reg modulus_mem_api_rst;
+ reg modulus_mem_api_cs;
+ reg modulus_mem_api_wr;
+
+ reg exponent_mem_api_rst;
+ reg exponent_mem_api_cs;
+ reg exponent_mem_api_wr;
+
+ reg message_mem_api_rst;
+ reg message_mem_api_cs;
+ reg message_mem_api_wr;
+
+ reg result_mem_api_rst;
+ reg result_mem_api_cs;
+
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
@@ -331,52 +337,57 @@ module modexp(
.write_data(residue_opa_wr_data)
);
- blockmem2r1w modulus_mem(
- .clk(clk),
- .read_addr0(modulus_mem_int_rd_addr),
- .read_data0(modulus_mem_int_rd_data),
- .read_addr1(address[7 : 0]),
- .read_data1(modulus_mem_api_rd_data),
- .wr(modulus_mem_api_we),
- .write_addr(address[7 : 0]),
- .write_data(write_data)
- );
-
-
- blockmem2r1w message_mem(
- .clk(clk),
- .read_addr0(message_mem_int_rd_addr),
- .read_data0(message_mem_int_rd_data),
- .read_addr1(address[7 : 0]),
- .read_data1(message_mem_api_rd_data),
- .wr(message_mem_api_we),
- .write_addr(address[7 : 0]),
- .write_data(write_data)
- );
-
-
- blockmem2r1w exponent_mem(
- .clk(clk),
- .read_addr0(exponent_mem_int_rd_addr),
- .read_data0(exponent_mem_int_rd_data),
- .read_addr1(address[7 : 0]),
- .read_data1(exponent_mem_api_rd_data),
- .wr(exponent_mem_api_we),
- .write_addr(address[7 : 0]),
- .write_data(write_data)
- );
-
-
- blockmem2r1w result_mem(
- .clk(clk),
- .read_addr0(result_mem_int_rd_addr[7 : 0]),
- .read_data0(result_mem_int_rd_data),
- .read_addr1(address[7 : 0]),
- .read_data1(result_mem_api_rd_data),
- .wr(result_mem_int_we),
- .write_addr(result_mem_int_wr_addr),
- .write_data(result_mem_int_wr_data)
- );
+ blockmem2r1wptr modulus_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(modulus_mem_int_rd_addr),
+ .read_data0(modulus_mem_int_rd_data),
+ .read_data1(modulus_mem_api_rd_data),
+ .rst(modulus_mem_api_rst),
+ .cs(modulus_mem_api_cs),
+ .wr(modulus_mem_api_wr),
+ .write_data(write_data)
+ );
+
+
+ blockmem2r1wptr message_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(message_mem_int_rd_addr),
+ .read_data0(message_mem_int_rd_data),
+ .read_data1(message_mem_api_rd_data),
+ .rst(message_mem_api_rst),
+ .cs(message_mem_api_cs),
+ .wr(message_mem_api_wr),
+ .write_data(write_data)
+ );
+
+
+ blockmem2r1wptr exponent_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(exponent_mem_int_rd_addr),
+ .read_data0(exponent_mem_int_rd_data),
+ .read_data1(exponent_mem_api_rd_data),
+ .rst(exponent_mem_api_rst),
+ .cs(exponent_mem_api_cs),
+ .wr(exponent_mem_api_wr),
+ .write_data(write_data)
+ );
+
+
+ blockmem2rptr1w result_mem(
+ .clk(clk),
+ .reset_n(reset_n),
+ .read_addr0(result_mem_int_rd_addr[7 : 0]),
+ .read_data0(result_mem_int_rd_data),
+ .read_data1(result_mem_api_rd_data),
+ .rst(result_mem_api_rst),
+ .cs(result_mem_api_cs),
+ .wr(result_mem_int_we),
+ .write_addr(result_mem_int_wr_addr),
+ .write_data(result_mem_int_wr_data)
+ );
blockmem2r1w p_mem(
.clk(clk),
@@ -410,7 +421,7 @@ module modexp(
modexp_ctrl_reg <= CTRL_IDLE;
one_reg <= 32'h0;
b_one_reg <= 32'h0;
- length_reg <= 8'h0;
+ length_reg <= DEFAULT_MODLENGTH;
length_m1_reg <= 8'h0;
loop_counter_reg <= 13'b0;
ei_reg <= 1'b0;
@@ -419,9 +430,9 @@ module modexp(
end
else
begin
- one_reg <= one_new;
- b_one_reg <= b_one_new;
- residue_valid_reg <= residue_valid_new;
+ one_reg <= one_new;
+ b_one_reg <= b_one_new;
+ residue_valid_reg <= residue_valid_new;
if (exponent_length_we)
exponent_length_reg <= exponent_length_new;
@@ -473,12 +484,25 @@ module modexp(
exponent_length_we = 1'b0;
start_new = 1'b0;
start_we = 1'b0;
- modulus_mem_api_we = 1'b0;
- exponent_mem_api_we = 1'b0;
- message_mem_api_we = 1'b0;
length_we = 1'b0;
invalidate_residue = 1'b0;
+ modulus_mem_api_rst = 1'b0;
+ modulus_mem_api_cs = 1'b0;
+ modulus_mem_api_wr = 1'b0;
+
+ exponent_mem_api_rst = 1'b0;
+ exponent_mem_api_cs = 1'b0;
+ exponent_mem_api_wr = 1'b0;
+
+ message_mem_api_rst = 1'b0;
+ message_mem_api_cs = 1'b0;
+ message_mem_api_wr = 1'b0;
+
+ result_mem_api_rst = 1'b0;
+ result_mem_api_cs = 1'b0;
+
+
//TODO: Add API code to enable fast exponation for working with public exponents.
exponation_mode_we = 1'b0;
@@ -512,19 +536,58 @@ module modexp(
start_we = 1'b1;
end
+ ADDR_MODULUS_LENGTH:
+ begin
+ modulus_length_we = 1'b1;
+ end
+
+ ADDR_EXPONENT_LENGTH:
+ begin
+ exponent_length_we = 1'b1;
+ end
+
ADDR_LENGTH:
begin
length_we = 1'b1;
end
- ADDR_MODULUS_LENGTH:
+ ADDR_MODULUS_PTR_RST:
begin
- modulus_length_we = 1'b1;
+ modulus_mem_api_rst = 1'b1;
end
- ADDR_EXPONENT_LENGTH:
+ ADDR_MODULUS_DATA:
begin
- exponent_length_we = 1'b1;
+ modulus_mem_api_cs = 1'b1;
+ modulus_mem_api_wr = 1'b1;
+ invalidate_residue = 1'b1;
+ end
+
+ ADDR_EXPONENT_PTR_RST:
+ begin
+ exponent_mem_api_rst = 1'b1;
+ end
+
+ ADDR_EXPONENT_DATA:
+ begin
+ exponent_mem_api_cs = 1'b1;
+ exponent_mem_api_wr = 1'b1;
+ end
+
+ ADDR_MESSAGE_PTR_RST:
+ begin
+ message_mem_api_rst = 1'b1;
+ end
+
+ ADDR_MESSAGE_DATA:
+ begin
+ message_mem_api_cs = 1'b1;
+ message_mem_api_wr = 1'b1;
+ end
+
+ ADDR_RESULT_PTR_RST:
+ begin
+ result_mem_api_rst = 1'b1;
end
default:
@@ -559,53 +622,35 @@ module modexp(
ADDR_LENGTH:
tmp_read_data = {24'h000000, length_reg};
- default:
+ ADDR_MODULUS_DATA:
begin
+ modulus_mem_api_cs = 1'b1;
+ tmp_read_data = modulus_mem_api_rd_data;
end
- endcase // case (address[7 : 0])
- end
- end
- MODULUS_PREFIX:
- begin
- if (we)
- begin
- modulus_mem_api_we = 1'b1;
- invalidate_residue = 1'b1;
- end
- else
- begin
- tmp_read_data = modulus_mem_api_rd_data;
- end
- end
+ ADDR_EXPONENT_DATA:
+ begin
+ exponent_mem_api_cs = 1'b1;
+ tmp_read_data = exponent_mem_api_rd_data;
+ end
- EXPONENT_PREFIX:
- begin
- if (we)
- begin
- exponent_mem_api_we = 1'b1;
- end
- else
- begin
- tmp_read_data = exponent_mem_api_rd_data;
- end
- end
+ ADDR_MESSAGE_DATA:
+ begin
+ message_mem_api_cs = 1'b1;
+ tmp_read_data = message_mem_api_rd_data;
+ end
- MESSAGE_PREFIX:
- begin
- if (we)
- begin
- message_mem_api_we = 1'b1;
- end
- else
- begin
- tmp_read_data = message_mem_api_rd_data;
- end
- end
+ ADDR_RESULT_DATA:
+ begin
+ result_mem_api_cs = 1'b1;
+ tmp_read_data = result_mem_api_rd_data;
+ end
- RESULT_PREFIX:
- begin
- tmp_read_data = result_mem_api_rd_data;
+ default:
+ begin
+ end
+ endcase // case (address[7 : 0])
+ end
end
default: