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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-25 09:42:31 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-25 09:42:31 +0200
commit97976d1f01665b9d5b5469ad4b43d275824a41d9 (patch)
tree45b48946eac798675a05b47dc7be998a621b58fe /src/rtl
parentfe04c613bc0c6d687270cd33b8dde8e853f6e9a4 (diff)
Added another state for setting s_mem_read_addr to allow shortcutting one cycle in each loop.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/montprod.v5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 6959833..ee87b97 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -319,6 +319,11 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
s_mem_read_addr = length_m1;
end
+ CTRL_LOOP_BQ:
+ begin
+ s_mem_read_addr = length_m1;
+ end
+
CTRL_CALC_ADD:
begin
//s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.