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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-18 11:16:56 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-18 11:16:56 +0200
commit90337c66cc1a644b27a4ed8e188b1aa4e07fea67 (patch)
tree193b8ce221626972b9214976464fef870ef2de6d /src/rtl
parent98e5f8c715090e54e057198c8e12cd133f37c4ce (diff)
Moved s logic mux control to control fsm.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/montprod.v12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 8f2d012..465bd70 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -332,28 +332,24 @@ module montprod(
always @*
begin : s_select_write
shr_carry_in_new = 1'b0;
- s_mux_new = SMUX_0;
s_mem_we_new = 1'b0;
sa_adder_data_in = 32'h0;
case (montprod_ctrl_reg)
CTRL_INIT_S:
begin
- s_mux_new = SMUX_0; // write 0
s_mem_we_new = 1'b1;
end
CTRL_L_CALC_SA:
begin
//s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
- s_mux_new = SMUX_ADD_SA;
s_mem_we_new = b_reg | q_reg;
end
CTRL_L_CALC_SDIV2:
begin
//s = (s + q*M + b*A) >>> 1; s>>=1. Takes (1..length) cycles.
- s_mux_new = SMUX_SHR;
s_mem_we_new = 1'b1;
end
@@ -459,6 +455,8 @@ module montprod(
b_bit_index_we = 1'b0;
bq_we = 1'b0;
+ s_mux_new = SMUX_0;
+
reset_word_index_lsw = 1'b0;
reset_word_index_msw = 1'b0;
@@ -483,6 +481,8 @@ module montprod(
CTRL_INIT_S:
begin
+ s_mux_new = SMUX_0; // write 0
+
if (word_index_reg == 8'h0)
begin
loop_ctr_set = 1'b1;
@@ -517,6 +517,8 @@ module montprod(
CTRL_L_CALC_SA:
begin
+ s_mux_new = SMUX_ADD_SA;
+
if (word_index_reg == 8'h0)
begin
reset_word_index_lsw = 1'b1;
@@ -534,6 +536,8 @@ module montprod(
CTRL_L_CALC_SDIV2:
begin
+ s_mux_new = SMUX_SHR;
+
if (word_index_reg == length_m1)
begin
montprod_ctrl_new = CTRL_L_STALLPIPE_D2;