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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-23 17:05:53 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-23 17:05:53 +0200
commit708b71fdd50f7dd3c6851b5c47a559968767c0db (patch)
tree65df7630f38c7e4330dfa338cb79d796c64ff984 /src/rtl
parentfeeb054a16bbb3ed6111ac2a165c6266b20750cb (diff)
Fixed incorrect compile time expression for sizing the memory.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/blockmem1r1w.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v
index 6a28cc2..6856e0a 100644
--- a/src/rtl/blockmem1r1w.v
+++ b/src/rtl/blockmem1r1w.v
@@ -54,7 +54,7 @@ module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
input wire [(OPW - 1) : 0] write_data
);
- reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)];
+ reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data;
assign read_data = tmp_read_data;