Changing module interface and internal defines to use symbolic widths for operand data size and addresses. We need to update counters too.

1 files changed, 82 insertions, 79 deletions

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 93ddacf..0a7b003 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -36,27 +36,28 @@
 //
 //======================================================================
 
-module montprod(
-                input wire           clk,
-                input wire           reset_n,
+module montprod #(parameter OPW = 32, parameter ADW = 8)
+               (
+                input wire                  clk,
+                input wire                  reset_n,
 
-                input wire           calculate,
-                output wire          ready,
+                input wire                  calculate,
+                output wire                 ready,
 
-                input   [7 : 0]      length,
+                input   [(ADW - 1) : 0]     length,
 
-                output wire [7 : 0]  opa_addr,
-                input wire [31 : 0]  opa_data,
+                output wire [(ADW - 1) : 0] opa_addr,
+                input wire [(OPW - 1) : 0]  opa_data,
 
-                output wire [7 : 0]  opb_addr,
-                input wire [31 : 0]  opb_data,
+                output wire [(ADW - 1) : 0] opb_addr,
+                input wire [(OPW - 1) : 0]  opb_data,
 
-                output wire [7 : 0]  opm_addr,
-                input wire [31 : 0]  opm_data,
+                output wire [(ADW - 1) : 0] opm_addr,
+                input wire [(OPW - 1) : 0]  opm_data,
 
-                output wire [7 : 0]  result_addr,
-                output wire [31 : 0] result_data,
-                output wire          result_we
+                output wire [(ADW - 1) : 0] result_addr,
+                output wire [(OPW - 1) : 0] result_data,
+                output wire                 result_we
                );
 
 
@@ -83,85 +84,85 @@ module montprod(
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
-  reg [07 : 0] opa_addr_reg;
-  reg [07 : 0] opb_addr_reg;
-  reg [07 : 0] opm_addr_reg;
+  reg [(ADW - 1) : 0]  opa_addr_reg;
+  reg [(ADW - 1) : 0]  opb_addr_reg;
+  reg [(ADW - 1) : 0]  opm_addr_reg;
 
-  reg [07 : 0] result_addr_reg;
-  reg [31 : 0] result_data_reg;
+  reg [(ADW - 1) : 0]  result_addr_reg;
+  reg [(OPW - 1) : 0]  result_data_reg;
 
-  reg          ready_reg;
-  reg          ready_new;
-  reg          ready_we;
+  reg                  ready_reg;
+  reg                  ready_new;
+  reg                  ready_we;
 
-  reg [3 : 0]  montprod_ctrl_reg;
-  reg [3 : 0]  montprod_ctrl_new;
-  reg          montprod_ctrl_we;
+  reg [3 : 0]          montprod_ctrl_reg;
+  reg [3 : 0]          montprod_ctrl_new;
+  reg                  montprod_ctrl_we;
 
-  reg  [1 : 0] s_mux_new;
-  reg  [1 : 0] s_mux_reg;
+  reg  [1 : 0]         s_mux_new;
+  reg  [1 : 0]         s_mux_reg;
 
-  reg [31 : 0]  s_mem_new;
-  reg           s_mem_we_reg;
-  reg           s_mem_we_new;
-  reg [07 : 0]  s_mem_addr;
-  reg [07 : 0]  s_mem_wr_addr_reg;
-  wire [31 : 0] s_mem_read_data;
+  reg [(OPW - 1) : 0]  s_mem_new;
+  reg                  s_mem_we_reg;
+  reg                  s_mem_we_new;
+  reg [(ADW - 1) : 0]  s_mem_addr;
+  reg [(ADW - 1) : 0]  s_mem_wr_addr_reg;
+  wire [(OPW - 1) : 0] s_mem_read_data;
 
-  reg           q_new;
-  reg           q_reg;
-  reg           b_new;
-  reg           b_reg;
-  reg           bq_we;
+  reg                  q_new;
+  reg                  q_reg;
+  reg                  b_new;
+  reg                  b_reg;
+  reg                  bq_we;
 
-  reg [12 : 0] loop_ctr_reg;
-  reg [12 : 0] loop_ctr_new;
-  reg          loop_ctr_we;
-  reg          loop_ctr_set;
-  reg          loop_ctr_dec;
+  reg [12 : 0]         loop_ctr_reg;
+  reg [12 : 0]         loop_ctr_new;
+  reg                  loop_ctr_we;
+  reg                  loop_ctr_set;
+  reg                  loop_ctr_dec;
 
-  reg [07 : 0] b_word_index; //loop counter as a word index
+  reg [(ADW - 1) : 0]  b_word_index; //loop counter as a word index
 
-  reg [04 : 0] b_bit_index_reg;
-  reg [04 : 0] b_bit_index_new;
-  reg          b_bit_index_we;
+  reg [04 : 0]         b_bit_index_reg;
+  reg [04 : 0]         b_bit_index_new;
+  reg                  b_bit_index_we;
 
-  reg [07 : 0] word_index_reg; //register of what word is being read
-  reg [07 : 0] word_index_new; //calculation of what word to be read
-  reg [07 : 0] word_index_prev_reg; //register of what word was read previously (result address to emit)
-  reg [07 : 0] length_m1;
+  reg [(ADW - 1) : 0]  word_index_reg;
+  reg [(ADW - 1) : 0]  word_index_new;
+  reg [(ADW - 1) : 0]  word_index_prev_reg;
+  reg [(ADW - 1) : 0]  length_m1;
 
-  reg          add_carry_in_sa_reg;
-  reg          add_carry_in_sa_new;
-  reg          add_carry_in_sm_reg;
-  reg          add_carry_in_sm_new;
+  reg                  add_carry_in_sa_reg;
+  reg                  add_carry_in_sa_new;
+  reg                  add_carry_in_sm_reg;
+  reg                  add_carry_in_sm_new;
 
-  reg          shr_carry_in_reg;
-  reg          shr_carry_in_new;
+  reg                  shr_carry_in_reg;
+  reg                  shr_carry_in_new;
 
-  reg          first_iteration_reg;
-  reg          first_iteration_new;
-  reg          first_iteration_we;
+  reg                  first_iteration_reg;
+  reg                  first_iteration_new;
+  reg                  first_iteration_we;
 
 
   //----------------------------------------------------------------
   // Wires.
   //----------------------------------------------------------------
-  reg           tmp_result_we;
-  wire [31 : 0] add_result_sa;
-  wire          add_carry_out_sa;
-  wire [31 : 0] add_result_sm;
-  wire          add_carry_out_sm;
+  reg                  tmp_result_we;
+  wire [(OPW - 1) : 0] add_result_sa;
+  wire                 add_carry_out_sa;
+  wire [(OPW - 1) : 0] add_result_sm;
+  wire                 add_carry_out_sm;
 
-  reg  [31 : 0] shr_data_in;
-  wire          shr_carry_out;
-  wire [31 : 0] shr_data_out;
+  reg  [(OPW - 1) : 0] shr_data_in;
+  wire                 shr_carry_out;
+  wire [(OPW - 1) : 0] shr_data_out;
 
-  reg           reset_word_index_lsw;
-  reg           reset_word_index_msw;
+  reg                  reset_word_index_lsw;
+  reg                  reset_word_index_msw;
 
-  reg [31 : 0]  sa_adder_data_in;
-  reg [31 : 0]  muxed_s_mem_read_data;
+  reg [(OPW - 1) : 0]  sa_adder_data_in;
+  reg [(OPW - 1) : 0]  muxed_s_mem_read_data;
 
 
 
@@ -379,8 +380,10 @@ module montprod(
               s_mem_new = add_result_sa;
             else if (q_reg)
               s_mem_new = add_result_sm;
+            else if (first_iteration_reg)
+              s_mem_new = 32'h0;
             else
-              s_mem_new = muxed_s_mem_read_data;
+              s_mem_new = s_mem_read_data;
 
             add_carry_in_sa_new = add_carry_out_sa;
             add_carry_in_sm_new = add_carry_out_sm;
@@ -468,10 +471,10 @@ module montprod(
           begin
             if (calculate)
               begin
-                ready_new            = 1'b0;
-                ready_we             = 1'b1;
                 first_iteration_new  = 1'b1;
                 first_iteration_we   = 1'b1;
+                ready_new            = 1'b0;
+                ready_we             = 1'b1;
                 reset_word_index_lsw = 1'b1;
                 montprod_ctrl_new    = CTRL_INIT_S;
                 montprod_ctrl_we     = 1'b1;
@@ -519,8 +522,6 @@ module montprod(
             if (word_index_reg == 8'h0)
               begin
                 reset_word_index_lsw = 1'b1;
-                first_iteration_new  = 1'b0;
-                first_iteration_we   = 1'b1;
                 montprod_ctrl_new    = CTRL_STALLPIPE_ADD;
                 montprod_ctrl_we     = 1'b1;
               end
@@ -528,9 +529,11 @@ module montprod(
 
         CTRL_STALLPIPE_ADD:
           begin
+            first_iteration_new  = 1'b0;
+            first_iteration_we   = 1'b1;
+            reset_word_index_msw = 1'b1;
             montprod_ctrl_new    = CTRL_CALC_SDIV2;
             montprod_ctrl_we     = 1'b1;
-            reset_word_index_msw = 1'b1;
           end
 
         CTRL_CALC_SDIV2: