Made the adder and shifters words size generic. Updated the montprod and residue to use the generic adder and shifters.

1 files changed, 30 insertions, 31 deletions

diff --git a/src/rtl/residue.v b/src/rtl/residue.v
index 3fa1666..ccfaeda 100644
--- a/src/rtl/residue.v
+++ b/src/rtl/residue.v
@@ -45,26 +45,26 @@
 //
 //======================================================================
 
-module residue(
-  input wire clk,
-  input wire reset_n,
+module residue #(parameter OPW = 32, parameter ADW = 8)
+              (
+               input wire clk,
+               input wire reset_n,
 
-  input wire  calculate,
-  output wire ready,
+               input wire  calculate,
+               output wire ready,
 
-  input wire  [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
-  input wire  [07 : 0] length,
+               input wire  [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
+               input wire  [07 : 0] length,
 
-  output wire [07 : 0] opa_rd_addr,
-  input wire  [31 : 0] opa_rd_data,
-  output wire [07 : 0] opa_wr_addr,
-  output wire [31 : 0] opa_wr_data,
-  output wire          opa_wr_we,
+               output wire [07 : 0] opa_rd_addr,
+               input wire  [31 : 0] opa_rd_data,
+               output wire [07 : 0] opa_wr_addr,
+               output wire [31 : 0] opa_wr_data,
+               output wire          opa_wr_we,
 
-  output wire [07 : 0] opm_addr,
-  input wire  [31 : 0] opm_data
-
-);
+               output wire [07 : 0] opm_addr,
+               input wire  [31 : 0] opm_data
+              );
 
 //----------------------------------------------------------------
 // Internal constant and parameter definitions.
@@ -143,21 +143,20 @@ assign ready       = ready_reg;
   //----------------------------------------------------------------
   // Instantions
   //----------------------------------------------------------------
-  adder32 subcmp(
-    .a(opa_rd_data),
-    .b( ~ opm_data),
-    .carry_in(sub_carry_in_reg),
-    .sum(sub_data),
-    .carry_out(sub_carry_out)
-  );
-
-  shl32 shl(
-    .a(opa_rd_data),
-    .carry_in(shl_carry_in_reg),
-    .amul2(shl_data),
-    .carry_out(shl_carry_out)
-  );
-
+  adder #(.OPW(OPW)) add_inst(
+                              .a(opa_rd_data),
+                              .b( ~ opm_data),
+                              .carry_in(sub_carry_in_reg),
+                              .sum(sub_data),
+                              .carry_out(sub_carry_out)
+                             );
+
+  shl #(.OPW(OPW)) shl_inst(
+                            .a(opa_rd_data),
+                            .carry_in(shl_carry_in_reg),
+                            .amul2(shl_data),
+                            .carry_out(shl_carry_out)
+                           );
 
 
   //----------------------------------------------------------------