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author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-22 22:12:20 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-06-22 22:12:20 +0200 |
commit | 5a0a6f87f2f63f9f1044725db0cac212c63f1fd6 (patch) | |
tree | f6d163325f49379043907ef529877785fbfe653f /src/rtl/blockmem1r1w.v | |
parent | a66de21d53a0bf2565dd9647ed49c4bdb84e2f11 (diff) |
Changed blockmem1r1w used in montprod to generic data and address widths. Updated instantiation to use generics.
Diffstat (limited to 'src/rtl/blockmem1r1w.v')
-rw-r--r-- | src/rtl/blockmem1r1w.v | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v index 1d84369..edff8dd 100644 --- a/src/rtl/blockmem1r1w.v +++ b/src/rtl/blockmem1r1w.v @@ -7,6 +7,9 @@ // // The memory is used in the modexp core. // +// paremeter OPW is operand word width in bits. +// parameter ADW is address width in bits. +// // // Author: Joachim Strombergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. @@ -39,19 +42,20 @@ // //====================================================================== -module blockmem1r1w( +module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8) + ( input wire clk, - input wire [07 : 0] read_addr, - output wire [31 : 0] read_data, + input wire [(ADW - 1) : 0] read_addr, + output wire [(OPW - 1) : 0] read_data, - input wire wr, - input wire [07 : 0] write_addr, - input wire [31 : 0] write_data + input wire wr, + input wire [(ADW - 1) : 0] write_addr, + input wire [(OPW - 1) : 0] write_data ); - reg [31 : 0] mem [0 : 255]; - reg [31 : 0] tmp_read_data; + reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)]; + reg [(OPW - 1) : 0] tmp_read_data; assign read_data = tmp_read_data; |