diff options
author | Joachim Strömbergson <joachim@secworks.se> | 2015-06-23 16:58:45 +0200 |
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committer | Joachim Strömbergson <joachim@secworks.se> | 2015-06-23 16:58:45 +0200 |
commit | feeb054a16bbb3ed6111ac2a165c6266b20750cb (patch) | |
tree | 7fcf40e1c6b397520fa64fc5cc03ccbe6c375004 /src/rtl/adder32.v | |
parent | 435b905a9e1ca2d5cc1b6e5d25689773d19dcde4 (diff) |
Changed name of files to reflect that the adder and the shifters are now not specifically working on 32-bit operands. HEADSUP: This breaks builds that use the old file names.
Diffstat (limited to 'src/rtl/adder32.v')
-rw-r--r-- | src/rtl/adder32.v | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/src/rtl/adder32.v b/src/rtl/adder32.v deleted file mode 100644 index fa8ed8c..0000000 --- a/src/rtl/adder32.v +++ /dev/null @@ -1,64 +0,0 @@ -//====================================================================== -// -// adder.v -// ------- -// Adder with separate carry in and carry out. Used in the montprod -// amd residue modules of the modexp core. -// -// -// Author: Peter Magnusson, Joachim Strömbergson -// Copyright (c) 2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module adder #(parameter OPW = 32) - ( - input [(OPW - 1) : 0] a, - input [(OPW - 1) : 0] b, - input carry_in, - - output wire [(OPW - 1) : 0] sum, - output wire carry_out - ); - - reg [(OPW) : 0] adder_result; - - assign sum = adder_result[(OPW - 1) : 0]; - assign carry_out = adder_result[(OPW)]; - - always @* - begin - adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in}; - end - -endmodule // adder - -//====================================================================== -// EOF adder.v -//====================================================================== |