Update of montprod after test implementation with different operand sizes.

1 files changed, 3 insertions, 7 deletions

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index ee87b97..a0ca302 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -47,7 +47,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
                 input wire                  calculate,
                 output wire                 ready,
 
-                input   [(ADW - 1) : 0]     length,
+                input wire [(ADW - 1) : 0]  length,
 
                 output wire [(ADW - 1) : 0] opa_addr,
                 input wire [(OPW - 1) : 0]  opa_data,
@@ -319,11 +319,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
             s_mem_read_addr = length_m1;
           end
 
-        CTRL_LOOP_BQ:
-          begin
-            s_mem_read_addr = length_m1;
-          end
-
         CTRL_CALC_ADD:
           begin
             //s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
@@ -403,7 +398,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
      else
        q_new = s_mem_read_data[0] ^ (opa_data[0] & b_new);
 
-     b_bit_index_new = (2**(13 - ADW) - 1) - loop_ctr_reg[(13 - ADW - 1) : 0];
+     // B_bit_index      = 5'h1f - loop_counter[4:0];
+     b_bit_index_new = ((2**(13 - ADW)) - 1'b1) - loop_ctr_reg[(13 - ADW - 1) : 0];
      b_word_index    = loop_ctr_reg[12 : (13 - ADW)];
    end // bq