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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-26 14:41:49 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-06-26 14:41:49 +0200
commit97de1e03b8a69924bc577027d5b4d95cf497bf45 (patch)
tree3e6ff759569b45f7a477f80843d2fe71c3c5afeb
parentcef6c5bab7aef166dc46488fc2f85b5428fc8db2 (diff)
Adding hold register and bit combine to create final s_mem data with fused add and div.
-rw-r--r--src/rtl/montprod.v19
1 files changed, 14 insertions, 5 deletions
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 12260ac..4b93e57 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -141,6 +141,10 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
reg test_reg;
reg test_new;
+ reg [(OPW - 2) : 0] shr_data_out_reg;
+ reg shr_carry_out_reg;
+ reg shr_carry_out_new;
+
//----------------------------------------------------------------
// Wires.
@@ -167,6 +171,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
reg [(OPW - 1) : 0] sa_adder_data_in;
reg [(OPW - 1) : 0] muxed_s_mem_read_data;
+ reg [(OPW - 1) : 0] shifted_s_mem_write_data;
wire [(ADW - 1) : 0] length_m1;
@@ -221,7 +226,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
);
shr #(.OPW(OPW)) shifter(
- .a(s_mem_read_data),
+ .a(shr_data_in),
.carry_in(shr_carry_in_reg),
.adiv2(shr_data_out),
.carry_out(shr_carry_out)
@@ -246,6 +251,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
word_index_prev_reg <= {ADW{1'b0}};
add_carry_in_sa_reg <= 1'b0;
add_carry_in_sm_reg <= 1'b0;
+ shr_data_out_reg <= {(OPW - 1){1'b0}};
shr_carry_in_reg <= 1'b0;
b_reg <= 1'b0;
q_reg <= 1'b0;
@@ -269,6 +275,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
shr_carry_in_reg <= shr_carry_in_new;
add_carry_in_sa_reg <= add_carry_in_sa_new;
add_carry_in_sm_reg <= add_carry_in_sm_new;
+ shr_data_out_reg <= shr_data_out[(OPW - 2) : 0];
if (word_index_we)
word_index_reg <= word_index_new;
@@ -321,7 +328,6 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
tmp_s_mem_write_data = {OPW{1'b0}};
test_new = 1'b0;
-
case (montprod_ctrl_reg)
CTRL_LOOP_ITER:
begin
@@ -339,7 +345,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
CTRL_CALC_SDIV2:
begin
//s = (s + q*M + b*A) >>> 1; s>>=1. Takes (1..length) cycles.
- s_mem_we_new = 1'b1;
+ s_mem_we_new = 1'b1;
end
default:
@@ -364,18 +370,21 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
else
sa_adder_data_in = muxed_s_mem_read_data;
+
if (b_reg)
tmp_s_mem_write_data = add_result_sa;
else if (q_reg)
tmp_s_mem_write_data = add_result_sm;
else if (first_iteration_reg)
tmp_s_mem_write_data = {OPW{1'b0}};
- else
- tmp_s_mem_write_data = s_mem_read_data;
s_mem_write_data = tmp_s_mem_write_data;
add_carry_in_sa_new = add_carry_out_sa;
add_carry_in_sm_new = add_carry_out_sm;
+
+
+ shr_data_in = tmp_s_mem_write_data;
+ shifted_s_mem_write_data = {shr_carry_out ,shr_data_out_reg};
end
SMUX_SHR: