From ab4638f70ee846de7398a3d78d467a9551e508cf Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Tue, 7 Mar 2017 19:46:44 -0500 Subject: Promote code common to both ECDSA* cores to separate repository in core/ tree. Pavel's two ECDSA base point multiplier cores share a fair amount of code. Maintenance issues aside, the duplication confused the Xilinx synthesis tools if one tried to build a single bitstream containing both cores, so we've separated the common code out into this library. The selection of files in this library was done by comparing the rtl trees of the two original core repositories using "diff -rqws" and selecting the files which diff reported as being identical. Also dealt with some cosmetic issues (indentation, Windows-isms, etc). --- rtl/lowlevel/adder47_wrapper.v | 64 +++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'rtl/lowlevel/adder47_wrapper.v') diff --git a/rtl/lowlevel/adder47_wrapper.v b/rtl/lowlevel/adder47_wrapper.v index 1a0a18e..be5b1ee 100644 --- a/rtl/lowlevel/adder47_wrapper.v +++ b/rtl/lowlevel/adder47_wrapper.v @@ -2,7 +2,7 @@ // // adder47_wrapper.v // ----------------------------------------------------------------------------- -// Wrapper for 47-bit adder. +// Wrapper for 47-bit adder. // // Authors: Pavel Shatov // @@ -34,36 +34,36 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -//------------------------------------------------------------------------------ - -module adder47_wrapper - ( - input clk, // clock - input [46: 0] a, // operand input - input [46: 0] b, // operand input - output [46: 0] s // sum output - ); - - // - // Include Primitive Selector - // -`include "ecdsa_lowlevel_settings.v" - - - // - // Instantiate Vendor/Generic Primitive - // - `ADDER47_PRIMITIVE adder47_inst - ( - .clk(clk), - .a(a), - .b(b), - .s(s) - ); - - -endmodule - +//------------------------------------------------------------------------------ + +module adder47_wrapper + ( + input clk, // clock + input [46: 0] a, // operand input + input [46: 0] b, // operand input + output [46: 0] s // sum output + ); + + // + // Include Primitive Selector + // +`include "ecdsa_lowlevel_settings.v" + + + // + // Instantiate Vendor/Generic Primitive + // + `ADDER47_PRIMITIVE adder47_inst + ( + .clk(clk), + .a(a), + .b(b), + .s(s) + ); + + +endmodule + //------------------------------------------------------------------------------ // End-of-File -//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ -- cgit v1.2.3