From 628d1dc860eb236fddbf5bb5e400bd74817cc317 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Tue, 17 Apr 2018 14:46:33 +0300 Subject: Microcode for ECDH cores. --- rtl/curve/uop/uop_init_rom_ecdh.v | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 rtl/curve/uop/uop_init_rom_ecdh.v diff --git a/rtl/curve/uop/uop_init_rom_ecdh.v b/rtl/curve/uop/uop_init_rom_ecdh.v new file mode 100644 index 0000000..dc92f2a --- /dev/null +++ b/rtl/curve/uop/uop_init_rom_ecdh.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps + +module uop_init_rom_ecdh + ( + input wire clk, + input wire [ 5: 0] addr, + output reg [19: 0] data + ); + + + // + // Microcode + // +`include "../uop_ecdsa.v" + + + // + // Initialization Microprogram for ECDH Mode + // + always @(posedge clk) + + case (addr) + + 6'd00: data <= {OPCODE_MOV, UOP_SRC_G_X, UOP_SRC_DUMMY, UOP_DST_RX, UOP_EXEC_ALWAYS}; + 6'd01: data <= {OPCODE_MOV, UOP_SRC_G_Y, UOP_SRC_DUMMY, UOP_DST_RY, UOP_EXEC_ALWAYS}; + 6'd02: data <= {OPCODE_MOV, UOP_SRC_ONE, UOP_SRC_DUMMY, UOP_DST_RZ, UOP_EXEC_ALWAYS}; + + default: data <= {OPCODE_RDY, UOP_SRC_DUMMY, UOP_SRC_DUMMY, UOP_DST_DUMMY, UOP_EXEC_ALWAYS}; + + endcase + + +endmodule -- cgit v1.2.3