Promote code common to both ECDSA* cores to separate repository in core/ tree.

Pavel's two ECDSA base point multiplier cores share a fair amount of
code.  Maintenance issues aside, the duplication confused the Xilinx
synthesis tools if one tried to build a single bitstream containing
both cores, so we've separated the common code out into this library.

The selection of files in this library was done by comparing the rtl
trees of the two original core repositories using "diff -rqws" and
selecting the files which diff reported as being identical.

Also dealt with some cosmetic issues (indentation, Windows-isms, etc).

1 files changed, 53 insertions, 53 deletions

diff --git a/rtl/lowlevel/artix7/mac16_artix7.v b/rtl/lowlevel/artix7/mac16_artix7.v
index 63b74ab..421e7ba 100644
--- a/rtl/lowlevel/artix7/mac16_artix7.v
+++ b/rtl/lowlevel/artix7/mac16_artix7.v
@@ -2,7 +2,7 @@
 //
 // mac16_artix7.v
 // -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 16-bit multiplier and 47-bit accumulator.

+// Hardware (Artix-7 DSP48E1) 16-bit multiplier and 47-bit accumulator.
 //
 // Authors: Pavel Shatov
 //
@@ -34,57 +34,57 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 //
-//------------------------------------------------------------------------------

-

-module mac16_artix7

-	(

-		input					clk,		// clock

-		input					clr,		// clear accumulator (active-high)

-		input					ce,		// enable clock (active-high)

-		input		[15: 0]	a,			// operand input

-		input		[15: 0]	b,			// operand input

-		output	[46: 0]	s			// sum output

-	);

-	

-			

-		//

-		// DSP48E1 Slice

-		//

-		

-		/* Operation Mode */

-	wire	[ 3: 0]	dsp48e1_alumode	= 4'b0000;

-	wire	[ 6: 0]	dsp48e1_opmode		= {2'b01, clr, 4'b0101};

-		

-		/* Internal Product */

-	wire	[47: 0]	p_int;

-

-	dsp48e1_wrapper dsp_adder

-	(

-		.clk			(clk),

-		

-		.ce			(ce),

-		

-		.carry		(1'b0),

-		

-		.alumode		(dsp48e1_alumode),

-		.opmode		(dsp48e1_opmode),

-		

-		.a				({{14{1'b0}}, a}),

-		.b				({{ 2{1'b0}}, b}),

-		.c				({48{1'b0}}),

-		

-		.p				(p_int)

-	);

-

-		//

-		// Output Mapping

-		//

-	assign s = p_int[46:0];

-	

-

-endmodule

-

-

+//------------------------------------------------------------------------------
+
+module mac16_artix7
+  (
+   input 	  clk, // clock
+   input 	  clr, // clear accumulator (active-high)
+   input 	  ce, // enable clock (active-high)
+   input [15: 0]  a, // operand input
+   input [15: 0]  b, // operand input
+   output [46: 0] s			// sum output
+   );
+
+
+   //
+   // DSP48E1 Slice
+   //
+
+   /* Operation Mode */
+   wire [ 3: 0]   dsp48e1_alumode	= 4'b0000;
+   wire [ 6: 0]   dsp48e1_opmode		= {2'b01, clr, 4'b0101};
+
+   /* Internal Product */
+   wire [47: 0]   p_int;
+
+   dsp48e1_wrapper dsp_adder
+     (
+      .clk			(clk),
+
+      .ce			(ce),
+
+      .carry		(1'b0),
+
+      .alumode		(dsp48e1_alumode),
+      .opmode		(dsp48e1_opmode),
+
+      .a				({{14{1'b0}}, a}),
+      .b				({{ 2{1'b0}}, b}),
+      .c				({48{1'b0}}),
+
+      .p				(p_int)
+      );
+
+   //
+   // Output Mapping
+   //
+   assign s = p_int[46:0];
+
+
+endmodule
+
+
 //------------------------------------------------------------------------------
 // End-of-File
-//------------------------------------------------------------------------------

+//------------------------------------------------------------------------------