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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-12-19 15:30:10 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-12-19 15:30:10 +0300
commit21cc313097a670403d5740177e20209b1f0388ae (patch)
tree43431201d5275d89cd73c22b6c213735a793b7a2 /rtl/curve/uop/uop_init_rom.v
parent628d1dc860eb236fddbf5bb5e400bd74817cc317 (diff)
Adapted for new ECDSA architecture.HEADmaster
Diffstat (limited to 'rtl/curve/uop/uop_init_rom.v')
-rw-r--r--rtl/curve/uop/uop_init_rom.v33
1 files changed, 0 insertions, 33 deletions
diff --git a/rtl/curve/uop/uop_init_rom.v b/rtl/curve/uop/uop_init_rom.v
deleted file mode 100644
index 0142c4c..0000000
--- a/rtl/curve/uop/uop_init_rom.v
+++ /dev/null
@@ -1,33 +0,0 @@
-`timescale 1ns / 1ps
-
-module uop_init_rom
- (
- input wire clk,
- input wire [ 5: 0] addr,
- output reg [19: 0] data
- );
-
-
- //
- // Microcode
- //
-`include "../uop_ecdsa.v"
-
-
- //
- // Initialization Microprogram
- //
- always @(posedge clk)
-
- case (addr)
-
- 6'd00: data <= {OPCODE_MOV, UOP_SRC_ONE, UOP_SRC_DUMMY, UOP_DST_RX, UOP_EXEC_ALWAYS};
- 6'd01: data <= {OPCODE_MOV, UOP_SRC_ONE, UOP_SRC_DUMMY, UOP_DST_RY, UOP_EXEC_ALWAYS};
- 6'd02: data <= {OPCODE_MOV, UOP_SRC_ZERO, UOP_SRC_DUMMY, UOP_DST_RZ, UOP_EXEC_ALWAYS};
-
- default: data <= {OPCODE_RDY, UOP_SRC_DUMMY, UOP_SRC_DUMMY, UOP_DST_DUMMY, UOP_EXEC_ALWAYS};
-
- endcase
-
-
-endmodule