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module bram_1wo_1ro_readfirst #
(
    parameter MEM_WIDTH     = 32,
    parameter MEM_ADDR_BITS =  8
)
(
    input   clk,

    input  [MEM_ADDR_BITS-1:0] a_addr,
    input                      a_wr,
    input  [MEM_WIDTH    -1:0] a_in,
    output [MEM_WIDTH    -1:0] a_out,

    input  [MEM_ADDR_BITS-1:0] b_addr,
    output [MEM_WIDTH    -1:0] b_out
);


    //
    // BRAM
    //
    (* RAM_STYLE="BLOCK" *)
    reg [MEM_WIDTH-1:0] bram[0:(2**MEM_ADDR_BITS)-1];


    //
    // Initialization for Simulation
    //
    /*
    integer c;
    initial begin
        for (c=0; c<(2**MEM_ADDR_BITS); c=c+1)
        bram[c] = {MEM_WIDTH{1'b0}};
    end
    */



    //
    // Output Registers
    //
    reg [MEM_WIDTH-1:0] bram_reg_b;

    assign a_out = 32'hDEADCE11;
    assign b_out = bram_reg_b;

    
    //
    // Note, that when both ports are accessing the same location, conflict can
    // potentionally arise. See Xilinx UG473 (pages 19-20, "Conflict
    // Avoidance") for more information. In our configuration to avoid that the
    // write port must be coded to operate in READ_FIRST mode. If the write
    // port is overwriting the same address the read port is accessing, the 
    // write port must read the previously stored data (not the data it is
    // writing, as that would be WRITE_FIRST mode).
    //


    //
    // Write-Only Port A
    //
    always @(posedge clk)
        //
        if (a_wr) bram[a_addr] <= a_in;


    //
    // Read-Only Port B
    //
    always @(posedge clk)
        //
        bram_reg_b <= bram[b_addr];


endmodule