From 057c4c6fe15b2fb5ef08397eef832620c3e6dead Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Fri, 9 Nov 2018 18:50:27 +0300 Subject: Library for common Verilog modules. --- lowlevel/generic/modexp_systolic_pe_generic.v | 85 +++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 lowlevel/generic/modexp_systolic_pe_generic.v (limited to 'lowlevel/generic/modexp_systolic_pe_generic.v') diff --git a/lowlevel/generic/modexp_systolic_pe_generic.v b/lowlevel/generic/modexp_systolic_pe_generic.v new file mode 100644 index 0000000..0e338ff --- /dev/null +++ b/lowlevel/generic/modexp_systolic_pe_generic.v @@ -0,0 +1,85 @@ +//====================================================================== +// +// modexp_systolic_pe_generic.v +// ----------------------------------------------------------------------------- +// Generic low-level systolic array processing element for ModExp core. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2017-2018, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module modexp_systolic_pe_generic + ( + input clk, + input [31: 0] a, + input [31: 0] b, + input [31: 0] t, + input [31: 0] c_in, + output [31: 0] p, + output [31: 0] c_out + ); + + // + // Customizable Latency + // + parameter LATENCY = 4; + + // + // Delay Line + // + reg [63: 0] abct[1:LATENCY]; + + // + // Outputs + // + assign p = abct[LATENCY][31: 0]; + assign c_out = abct[LATENCY][63:32]; + + // + // Sub-products + // + wire [63: 0] ab = {{32{1'b0}}, a} * {{32{1'b0}}, b}; + wire [63: 0] ct = {{32{1'b0}}, c_in} + {{32{1'b0}}, t}; + + // + // Delay + // + integer i; + always @(posedge clk) + // + for (i=1; i<=LATENCY; i=i+1) + abct[i] <= (i == 1) ? ab + ct : abct[i-1]; + +endmodule + +//====================================================================== +// End of file +//====================================================================== -- cgit v1.2.3