From fbcbd4218e2711da279d8097620a5b26637bf45b Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Wed, 19 Dec 2018 15:27:04 +0300 Subject: Added primitives with clock enable ports. Added primitives from ModExp. --- bench/tb_lowlevel_adder32.v | 175 +++++++++++++ bench/tb_lowlevel_adder47.v | 151 +++++++++++ bench/tb_lowlevel_subtractor32.v | 174 +++++++++++++ bench/tb_modular_adder.v | 357 +++++++++++++++++++++++++++ bench/tb_modular_subtractor.v | 356 ++++++++++++++++++++++++++ bench/tb_mw_comparator.v | 322 ++++++++++++++++++++++++ bench/tb_mw_mover.v | 282 +++++++++++++++++++++ lowlevel/artix7/adder32_ce_artix7.v | 97 ++++++++ lowlevel/artix7/dsp48e1_wrapper_modexp.v | 2 +- lowlevel/artix7/modexp_multiplier32_artix7.v | 171 +++++++++++++ lowlevel/artix7/modexp_systolic_pe_artix7.v | 11 +- lowlevel/artix7/subtractor32_ce_artix7.v | 95 +++++++ lowlevel/cryptech_primitive_switch.vh | 36 ++- lowlevel/generic/adder32_ce_generic.v | 68 +++++ lowlevel/generic/subtractor32_ce_generic.v | 68 +++++ 15 files changed, 2349 insertions(+), 16 deletions(-) create mode 100644 bench/tb_lowlevel_adder32.v create mode 100644 bench/tb_lowlevel_adder47.v create mode 100644 bench/tb_lowlevel_subtractor32.v create mode 100644 bench/tb_modular_adder.v create mode 100644 bench/tb_modular_subtractor.v create mode 100644 bench/tb_mw_comparator.v create mode 100644 bench/tb_mw_mover.v create mode 100644 lowlevel/artix7/adder32_ce_artix7.v create mode 100644 lowlevel/artix7/modexp_multiplier32_artix7.v create mode 100644 lowlevel/artix7/subtractor32_ce_artix7.v create mode 100644 lowlevel/generic/adder32_ce_generic.v create mode 100644 lowlevel/generic/subtractor32_ce_generic.v diff --git a/bench/tb_lowlevel_adder32.v b/bench/tb_lowlevel_adder32.v new file mode 100644 index 0000000..70fbb15 --- /dev/null +++ b/bench/tb_lowlevel_adder32.v @@ -0,0 +1,175 @@ +//------------------------------------------------------------------------------ +// +// tb_lowlevel_adder32.v +// ----------------------------------------------------------------------------- +// Testbench for 32-bit adder. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2015-2016, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +`timescale 1ns / 1ps +//------------------------------------------------------------------------------ + + +module tb_lowlevel_adder32; + + // + // Inputs + // + reg clk; + reg [31: 0] a; + reg [31: 0] b; + reg c_in; + + // + // Outputs + // + wire [31: 0] s; + wire c_out; + + // + // Test Vectors {a, b, c_in} + // + wire [64: 0] vec_0 = {32'h00000000, 32'h00000000, 1'b0}; // all zeroes, no carry + wire [64: 0] vec_1 = {32'h00000000, 32'h00000000, 1'b1}; // all zeroes with carry + wire [64: 0] vec_2 = {32'h00000000, 32'hFFFFFFFF, 1'b0}; // zeroes and ones, no carry + wire [64: 0] vec_3 = {32'h00000000, 32'hFFFFFFFF, 1'b1}; // zeroes and ones with carry + wire [64: 0] vec_4 = {32'hFFFFFFFF, 32'h00000000, 1'b0}; // ones and zeroes, no carry + wire [64: 0] vec_5 = {32'hFFFFFFFF, 32'h00000000, 1'b1}; // ones and zeroes with carry + wire [64: 0] vec_6 = {32'hFFFFFFFF, 32'hFFFFFFFF, 1'b0}; // all ones, no carry + wire [64: 0] vec_7 = {32'hFFFFFFFF, 32'hFFFFFFFF, 1'b1}; // all ones with carry + + wire [64: 0] vec_8 = {32'hd898c296, 32'h37bf51f5, 1'b0}; // random values, no carry + wire [64: 0] vec_9 = {32'hf4a13945, 32'hcbb64068, 1'b0}; // random values, no carry + wire [64: 0] vec_10 = {32'h2deb33a0, 32'h6b315ece, 1'b0}; // random values, no carry + wire [64: 0] vec_11 = {32'h77037d81, 32'h2bce3357, 1'b0}; // random values, no carry + wire [64: 0] vec_12 = {32'h63a440f2, 32'h7c0f9e16, 1'b1}; // random values with carry + wire [64: 0] vec_13 = {32'hf8bce6e5, 32'h8ee7eb4a, 1'b1}; // random values with carry + wire [64: 0] vec_14 = {32'he12c4247, 32'hfe1a7f9b, 1'b1}; // random values with carry + wire [64: 0] vec_15 = {32'h6b17d1f2, 32'h4fe342e2, 1'b1}; // random values with carry + + + // + // UUT + // + adder32_wrapper uut + ( + .clk (clk), + .a (a), + .b (b), + .s (s), + .c_in (c_in), + .c_out (c_out) + ); + + + // + // Testbench Routine + // + reg ok = 1; + initial begin + // + clk = 0; + // + #100; + // + test_adder32(vec_0); + test_adder32(vec_1); + test_adder32(vec_2); + test_adder32(vec_3); + test_adder32(vec_4); + test_adder32(vec_5); + test_adder32(vec_6); + test_adder32(vec_7); + // + test_adder32(vec_8); + test_adder32(vec_9); + test_adder32(vec_10); + test_adder32(vec_11); + test_adder32(vec_12); + test_adder32(vec_13); + test_adder32(vec_14); + test_adder32(vec_15); + // + if (ok) $display("tb_lowlevel_adder32: SUCCESS"); + else $display("tb_lowlevel_adder32: FAILURE"); + // + $finish; + // + end + + + // + // Test Routine + // + reg [31: 0] ss; // reference value of sum + reg cc; // reference value of carry + reg ss_ok; // result matches reference value + + task test_adder32; + + input [64: 0] vec; + + begin + + /* break down test vector */ + a = vec[64:33]; + b = vec[32: 1]; + c_in = vec[ 0: 0]; + + /* calculate reference values */ + {cc, ss} = {1'b0, a} + {1'b0, b} + {32'd0, c_in}; + + /* send one clock tick */ + #10 clk = 1; + #10 clk = 0; + + /* check outputs */ + ss_ok = (s == ss) && (c_out == cc); + + /* display results */ + $display("test_adder32(): 0x%08X + 0x%08X + %01d = {%01d, 0x%08X} [%0s]", a, b, c_in, c_out, s, ok ? "OK" : "ERROR"); + + /* update global flag */ + ok = ok && ss_ok; + + end + + endtask + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/bench/tb_lowlevel_adder47.v b/bench/tb_lowlevel_adder47.v new file mode 100644 index 0000000..663e8f9 --- /dev/null +++ b/bench/tb_lowlevel_adder47.v @@ -0,0 +1,151 @@ +//------------------------------------------------------------------------------ +// +// tb_lowlevel_adder47.v +// ----------------------------------------------------------------------------- +// Testbench for 47-bit adder. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +`timescale 1ns / 1ps +//------------------------------------------------------------------------------ + + +module tb_lowlevel_adder47; + + // + // Inputs + // + reg clk; + reg [46: 0] a; + reg [46: 0] b; + + // + // Outputs + // + wire [46: 0] s; + + // + // Test Vectors {a, b} + // + wire [93: 0] vec_0 = {47'h2a87ca22be8b, 47'h05378eb1c71e}; + wire [93: 0] vec_1 = {47'h7320ad746e1d, 47'h3b628ba79b98}; + wire [93: 0] vec_2 = {47'h59f741e08254, 47'h2a385502f25d}; + wire [93: 0] vec_3 = {47'h3f55296c3a54, 47'h5e3872760ab7}; + wire [93: 0] vec_4 = {47'h3617de4a9626, 47'h2c6f5d9e98bf}; + wire [93: 0] vec_5 = {47'h1292dc29f8f4, 47'h1dbd289a147c}; + wire [93: 0] vec_6 = {47'h69da3113b5f0, 47'h38c00a60b1ce}; + wire [93: 0] vec_7 = {47'h1d7e819d7a43, 47'h1d7c90ea0e5f}; + + // + // UUT + // + adder47_wrapper uut + ( + .clk (clk), + .a (a), + .b (b), + .s (s) + ); + + + // + // Testbench Routine + // + reg ok = 1; + initial begin + // + clk = 0; + // + #100; + // + test_adder47(vec_0); + test_adder47(vec_1); + test_adder47(vec_2); + test_adder47(vec_3); + test_adder47(vec_4); + test_adder47(vec_5); + test_adder47(vec_6); + test_adder47(vec_7); + // + if (ok) $display("tb_lowlevel_adder47: SUCCESS"); + else $display("tb_lowlevel_adder47: FAILURE"); + // + $finish; + // + end + + + // + // Test Routine + // + reg [46: 0] ss; // reference value of sum + reg cc; // reference value of carry + reg ss_ok; // result matches reference value + + task test_adder47; + + input [93: 0] vec; + + begin + + /* break down test vector */ + a = vec[93:47]; + b = vec[46: 0]; + + /* calculate reference values */ + ss = a + b; + + /* send one clock tick */ + #10 clk = 1; + #10 clk = 0; + + /* check outputs */ + ss_ok = (s == ss); + + /* display results */ + $display("test_adder47(): %s", ok ? "OK" : "ERROR"); + + /* update global flag */ + ok = ok && ss_ok; + + end + + endtask + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/bench/tb_lowlevel_subtractor32.v b/bench/tb_lowlevel_subtractor32.v new file mode 100644 index 0000000..fd96000 --- /dev/null +++ b/bench/tb_lowlevel_subtractor32.v @@ -0,0 +1,174 @@ +//------------------------------------------------------------------------------ +// +// tb_lowlevel_subtractor32.v +// ----------------------------------------------------------------------------- +// Testbench for 32-bit subtractor. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2015-2016, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +`timescale 1ns / 1ps +//------------------------------------------------------------------------------ + +module tb_lowlevel_subtractor32; + + // + // Inputs + // + reg clk; + reg [31: 0] a; + reg [31: 0] b; + reg b_in; + + // + // Outputs + // + wire [31: 0] d; + wire b_out; + + // + // Test Vectors {a, b, b_in} + // + wire [64: 0] vec_0 = {32'h00000000, 32'h00000000, 1'b0}; // all zeroes, no borrow + wire [64: 0] vec_1 = {32'h00000000, 32'h00000000, 1'b1}; // all zeroes with borrow + wire [64: 0] vec_2 = {32'h00000000, 32'hFFFFFFFF, 1'b0}; // zeroes and ones, no borrow + wire [64: 0] vec_3 = {32'h00000000, 32'hFFFFFFFF, 1'b1}; // zeroes and ones with borrow + wire [64: 0] vec_4 = {32'hFFFFFFFF, 32'h00000000, 1'b0}; // ones and zeroes, no borrow + wire [64: 0] vec_5 = {32'hFFFFFFFF, 32'h00000000, 1'b1}; // ones and zeroes with borrow + wire [64: 0] vec_6 = {32'hFFFFFFFF, 32'hFFFFFFFF, 1'b0}; // all ones, no borrow + wire [64: 0] vec_7 = {32'hFFFFFFFF, 32'hFFFFFFFF, 1'b1}; // all ones with borrow + + wire [64: 0] vec_8 = {32'hd898c296, 32'h37bf51f5, 1'b0}; // random values, no borrow + wire [64: 0] vec_9 = {32'hf4a13945, 32'hcbb64068, 1'b0}; // random values, no borrow + wire [64: 0] vec_10 = {32'h2deb33a0, 32'h6b315ece, 1'b0}; // random values, no borrow + wire [64: 0] vec_11 = {32'h77037d81, 32'h2bce3357, 1'b0}; // random values, no borrow + wire [64: 0] vec_12 = {32'h63a440f2, 32'h7c0f9e16, 1'b1}; // random values with borrow + wire [64: 0] vec_13 = {32'hf8bce6e5, 32'h8ee7eb4a, 1'b1}; // random values with borrow + wire [64: 0] vec_14 = {32'he12c4247, 32'hfe1a7f9b, 1'b1}; // random values with borrow + wire [64: 0] vec_15 = {32'h6b17d1f2, 32'h4fe342e2, 1'b1}; // random values with borrow + + + // + // UUT + // + subtractor32_wrapper uut + ( + .clk (clk), + .a (a), + .b (b), + .d (d), + .b_in (b_in), + .b_out (b_out) + ); + + + // + // Testbench Routine + // + reg ok = 1; + initial begin + // + clk = 0; + // + #100; + // + test_subtractor32(vec_0); + test_subtractor32(vec_1); + test_subtractor32(vec_2); + test_subtractor32(vec_3); + test_subtractor32(vec_4); + test_subtractor32(vec_5); + test_subtractor32(vec_6); + test_subtractor32(vec_7); + // + test_subtractor32(vec_8); + test_subtractor32(vec_9); + test_subtractor32(vec_10); + test_subtractor32(vec_11); + test_subtractor32(vec_12); + test_subtractor32(vec_13); + test_subtractor32(vec_14); + test_subtractor32(vec_15); + // + if (ok) $display("tb_lowlevel_subtractor32: SUCCESS"); + else $display("tb_lowlevel_subtractor32: FAILURE"); + // + $finish; + // + end + + + // + // Test Routine + // + reg [31: 0] dd; // reference value of difference + reg bb; // reference value of borrow + reg dd_ok; // result matches reference value + + task test_subtractor32; + + input [64: 0] vec; + + begin + + /* break down test vector */ + a = vec[64:33]; + b = vec[32: 1]; + b_in = vec[ 0: 0]; + + /* calculate reference values */ + {bb, dd} = {1'b0, a} - {1'b0, b} - {32'd0, b_in}; + + /* send one clock tick */ + #10 clk = 1; + #10 clk = 0; + + /* check outputs */ + dd_ok = (d == dd) && (b_out == bb); + + /* display results */ + $display("test_subtractor32(): 0x%08X - (0x%08X + %01d) = {%01d, 0x%08X} [%0s]", a, b, b_in, b_out, d, dd_ok ? "OK" : "ERROR"); + + /* update global flag */ + ok = ok && dd_ok; + + end + + endtask + +endmodule + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/bench/tb_modular_adder.v b/bench/tb_modular_adder.v new file mode 100644 index 0000000..713ff22 --- /dev/null +++ b/bench/tb_modular_adder.v @@ -0,0 +1,357 @@ +//------------------------------------------------------------------------------ +// +// tb_modular_adder_256.v +// ----------------------------------------------------------------------------- +// Testbench for modular multi-word adder. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +`timescale 1ns / 1ps +//------------------------------------------------------------------------------ + +module tb_modular_adder_256; + + + // + // Test Vectors + // + localparam [255:0] N = 256'hffffffff00000001000000000000000000000000ffffffffffffffffffffffff; + + localparam [255:0] X_1 = 256'h1ddbd0769df27bab1e234019dad09dccce1e87e2193b417ffa1a3465d7439ecd; + localparam [255:0] Y_1 = 256'h1f67cdc34bac91a072945d212f0a03442fc4855788583ecb7b2e375ad3848210; + + localparam [255:0] X_2 = 256'hff563f653b1392a6fa6b0295a280f7a904a11e22d8ae468e220301d8ac232fcf; + localparam [255:0] Y_2 = 256'hf6f53c4b57b25453b68e923fb118e4f753d74af01fc58476dd15a80933453899; + + + // + // Core Parameters + // + localparam WORD_COUNTER_WIDTH = 3; + localparam OPERAND_NUM_WORDS = 8; + + + // + // Clock (100 MHz) + // + reg clk = 1'b0; + always #5 clk = ~clk; + + + // + // Inputs, Outputs + // + reg rst_n; + reg ena; + wire rdy; + + + // + // Buffers (X, Y, N) + // + wire [WORD_COUNTER_WIDTH-1:0] core_xy_addr; + wire [WORD_COUNTER_WIDTH-1:0] core_n_addr; + wire [WORD_COUNTER_WIDTH-1:0] core_s_addr; + wire core_s_wren; + + wire [ 31:0] core_x_data; + wire [ 31:0] core_y_data; + wire [ 31:0] core_n_data; + wire [ 31:0] core_s_data; + + reg [WORD_COUNTER_WIDTH-1:0] tb_xyn_addr; + reg [WORD_COUNTER_WIDTH-1:0] tb_s_addr; + reg tb_xyn_wren; + + reg [ 31:0] tb_x_data; + reg [ 31:0] tb_y_data; + reg [ 31:0] tb_n_data; + wire [ 31:0] tb_s_data; + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH (32), + .MEM_ADDR_BITS (WORD_COUNTER_WIDTH) + ) + bram_x + ( + .clk (clk), + + .a_addr (tb_xyn_addr), + .a_wr (tb_xyn_wren), + .a_in (tb_x_data), + .a_out (), + + .b_addr (core_xy_addr), + .b_out (core_x_data) + ); + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH (32), + .MEM_ADDR_BITS (WORD_COUNTER_WIDTH) + ) + bram_y + ( + .clk (clk), + + .a_addr (tb_xyn_addr), + .a_wr (tb_xyn_wren), + .a_in (tb_y_data), + .a_out (), + + .b_addr (core_xy_addr), + .b_out (core_y_data) + ); + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH (32), + .MEM_ADDR_BITS (WORD_COUNTER_WIDTH) + ) + bram_n + ( + .clk (clk), + + .a_addr (tb_xyn_addr), + .a_wr (tb_xyn_wren), + .a_in (tb_n_data), + .a_out (), + + .b_addr (core_n_addr), + .b_out (core_n_data) + ); + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH (32), + .MEM_ADDR_BITS (WORD_COUNTER_WIDTH) + ) + bram_s + ( + .clk (clk), + + .a_addr (core_s_addr), + .a_wr (core_s_wren), + .a_in (core_s_data), + .a_out (), + + .b_addr (tb_s_addr), + .b_out (tb_s_data) + ); + + + // + // UUT + // + modular_adder # + ( + .WORD_COUNTER_WIDTH (WORD_COUNTER_WIDTH), + .OPERAND_NUM_WORDS (OPERAND_NUM_WORDS) + ) + uut + ( + .clk (clk), + .rst_n (rst_n), + + .ena (ena), + .rdy (rdy), + + .ab_addr (core_xy_addr), + .n_addr (core_n_addr), + .s_addr (core_s_addr), + .s_wren (core_s_wren), + + .a_din (core_x_data), + .b_din (core_y_data), + .n_din (core_n_data), + .s_dout (core_s_data) + ); + + + // + // Testbench Routine + // + reg ok = 1; + initial begin + + /* initialize control inputs */ + rst_n = 0; + ena = 0; + + tb_xyn_wren = 0; + + /* wait for some time */ + #200; + + /* de-assert reset */ + rst_n = 1; + + /* wait for some time */ + #100; + + /* run tests */ + test_modular_adder(X_1, Y_1, N); + test_modular_adder(X_2, Y_2, N); + test_modular_adder(Y_1, X_1, N); + test_modular_adder(Y_2, X_2, N); + + test_modular_adder(X_1, X_2, N); + test_modular_adder(X_2, X_1, N); + test_modular_adder(Y_1, Y_2, N); + test_modular_adder(Y_2, Y_1, N); + + test_modular_adder(X_1, Y_2, N); + test_modular_adder(Y_2, X_1, N); + test_modular_adder(X_2, Y_1, N); + test_modular_adder(Y_1, X_2, N); + + /* print result */ + if (ok) $display("tb_modular_adder_256: SUCCESS"); + else $display("tb_modular_adder_256: FAILURE"); + // + $finish; + // + end + + + // + // Test Task + // + reg [256:0] s; + wire [255:0] s_dummy = s[255:0]; + reg s_ok; + + integer w; + + reg [255:0] x_shreg; + reg [255:0] y_shreg; + reg [255:0] n_shreg; + reg [255:0] s_shreg; + + task test_modular_adder; + + input [255:0] x; + input [255:0] y; + input [255:0] n; + + begin + + /* start filling memories */ + tb_xyn_wren = 1; + + /* initialize shift registers */ + x_shreg = x; + y_shreg = y; + n_shreg = n; + + /* write all the words */ + for (w=0; w= {1'b0, n}) + s = s - {1'b0, n}; + + /* start operation */ + ena = 1; + + /* clear flag */ + #10 ena = 0; + + /* wait for operation to complete */ + while (!rdy) #10; + + /* read result */ + for (w=0; w y) ? 1 : 0; + + /* start operation */ + ena = 1; + + /* clear flag */ + #10 ena = 0; + + /* wait for operation to complete */ + while (!rdy) #10; + + /* compare */ + cmp_ok = (cmp_l == core_cmp_l) && (cmp_e == core_cmp_e) && (cmp_g == core_cmp_g); + + /* display results */ + $display("test_mw_comparator(): %s", cmp_ok ? "OK" : "ERROR"); + + /* update global flag */ + ok = ok && cmp_ok; + + end + + endtask + +endmodule + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ diff --git a/bench/tb_mw_mover.v b/bench/tb_mw_mover.v new file mode 100644 index 0000000..08bdb9e --- /dev/null +++ b/bench/tb_mw_mover.v @@ -0,0 +1,282 @@ +//------------------------------------------------------------------------------ +// +// tb_modular_mover.v +// ----------------------------------------------------------------------------- +// Testbench for multi-word data mover. +// +// Authors: Pavel Shatov +// +// Copyright (c) 2016, NORDUnet A/S +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may be +// used to endorse or promote products derived from this software without +// specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +`timescale 1ns / 1ps +//------------------------------------------------------------------------------ + +module tb_mw_mover; + + + // + // Test Vectors + // + localparam [255:0] X_1 = 256'h1ddbd0769df27bab1e234019dad09dccce1e87e2193b417ffa1a3465d7439ecd; + localparam [255:0] X_2 = 256'h1f67cdc34bac91a072945d212f0a03442fc4855788583ecb7b2e375ad3848210; + localparam [255:0] X_3 = 256'hff563f653b1392a6fa6b0295a280f7a904a11e22d8ae468e220301d8ac232fcf; + localparam [255:0] X_4 = 256'hf6f53c4b57b25453b68e923fb118e4f753d74af01fc58476dd15a80933453899; + + + // + // Core Parameters + // + localparam WORD_COUNTER_WIDTH = 3; + localparam OPERAND_NUM_WORDS = 8; + + + // + // Clock (100 MHz) + // + reg clk = 1'b0; + always #5 clk = ~clk; + + + // + // Inputs, Outputs + // + reg rst_n; + reg ena; + wire rdy; + + + // + // Buffers (X, Y) + // + wire [WORD_COUNTER_WIDTH-1:0] core_x_addr; + wire [WORD_COUNTER_WIDTH-1:0] core_y_addr; + wire core_y_wren; + + wire [ 32-1:0] core_x_data; + wire [ 32-1:0] core_y_data; + + reg [WORD_COUNTER_WIDTH-1:0] tb_x_addr; + reg [WORD_COUNTER_WIDTH-1:0] tb_y_addr; + reg tb_x_wren; + + reg [ 32-1:0] tb_x_data; + wire [ 32-1:0] tb_y_data; + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH (32), + .MEM_ADDR_BITS (WORD_COUNTER_WIDTH) + ) + bram_x + ( + .clk (clk), + + .a_addr (tb_x_addr), + .a_wr (tb_x_wren), + .a_in (tb_x_data), + .a_out (), + + .b_addr (core_x_addr), + .b_out (core_x_data) + ); + + bram_1rw_1ro_readfirst # + ( + .MEM_WIDTH (32), + .MEM_ADDR_BITS (WORD_COUNTER_WIDTH) + ) + bram_d + ( + .clk (clk), + + .a_addr (core_y_addr), + .a_wr (core_y_wren), + .a_in (core_y_data), + .a_out (), + + .b_addr (tb_y_addr), + .b_out (tb_y_data) + ); + + + // + // UUT + // + mw_mover # + ( + .WORD_COUNTER_WIDTH (WORD_COUNTER_WIDTH), + .OPERAND_NUM_WORDS (OPERAND_NUM_WORDS) + ) + uut + ( + .clk (clk), + .rst_n (rst_n), + + .ena (ena), + .rdy (rdy), + + .x_addr (core_x_addr), + .y_addr (core_y_addr), + .y_wren (core_y_wren), + + .x_din (core_x_data), + .y_dout (core_y_data) + ); + + + // + // Testbench Routine + // + reg ok = 1; + initial begin + + /* initialize control inputs */ + rst_n = 0; + ena = 0; + + tb_x_wren = 0; + + /* wait for some time */ + #200; + + /* de-assert reset */ + rst_n = 1; + + /* wait for some time */ + #100; + + /* run tests */ + test_modular_mover(X_1); + test_modular_mover(X_2); + test_modular_mover(X_3); + test_modular_mover(X_4); + + /* print result */ + if (ok) $display("tb_modular_mover: SUCCESS"); + else $display("tb_modular_mover: FAILURE"); + // + $finish; + // + end + + + // + // Test Task + // + reg [255:0] y; + reg y_ok; + + integer w; + + reg [255:0] x_shreg; + reg [255:0] y_shreg; + + task test_modular_mover; + + input [255:0] x; + + begin + + /* start filling memories */ + tb_x_wren = 1; + + /* initialize shift registers */ + x_shreg = x; + + /* write all the words */ + for (w=0; w