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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:27:04 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:27:04 +0300 |
| commit | fbcbd4218e2711da279d8097620a5b26637bf45b (patch) | |
| tree | 9f5a48a32fd9e30bfeb52db82fb0a11b418b7206 /lowlevel/artix7/dsp48e1_wrapper_modexp.v | |
| parent | 057c4c6fe15b2fb5ef08397eef832620c3e6dead (diff) | |
Added primitives with clock enable ports.
Added primitives from ModExp.
Diffstat (limited to 'lowlevel/artix7/dsp48e1_wrapper_modexp.v')
| -rw-r--r-- | lowlevel/artix7/dsp48e1_wrapper_modexp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lowlevel/artix7/dsp48e1_wrapper_modexp.v b/lowlevel/artix7/dsp48e1_wrapper_modexp.v index 17d8efe..27c8bf8 100644 --- a/lowlevel/artix7/dsp48e1_wrapper_modexp.v +++ b/lowlevel/artix7/dsp48e1_wrapper_modexp.v @@ -36,7 +36,7 @@ // //------------------------------------------------------------------------------ -module modexpa7_dsp48e1_wrapper_modexp # +module dsp48e1_wrapper_modexp # ( parameter AREG = 1'b0, parameter PREG = 1'b0, |