From 9ff1f0d496ec2049f4f564443106fc3ae5dfaaf8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sat, 18 Jul 2015 12:32:56 +0200 Subject: Added API logic to set write signals for the state. --- src/rtl/sha512.v | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'src') diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v index e1bf745..4b53e5b 100644 --- a/src/rtl/sha512.v +++ b/src/rtl/sha512.v @@ -663,6 +663,22 @@ module sha512( block29_we = 0; block30_we = 0; block31_we = 0; + state00_we = 0; + state01_we = 0; + state02_we = 0; + state03_we = 0; + state04_we = 0; + state05_we = 0; + state06_we = 0; + state07_we = 0; + state08_we = 0; + state09_we = 0; + state10_we = 0; + state11_we = 0; + state12_we = 0; + state13_we = 0; + state14_we = 0; + state15_we = 0; tmp_read_data = 32'h00000000; tmp_error = 0; @@ -847,6 +863,54 @@ module sha512( block31_we = 1; end + ADDR_DIGEST0: + state00_we = 1; + + ADDR_DIGEST1: + state01_we = 1; + + ADDR_DIGEST2: + state02_we = 1; + + ADDR_DIGEST3: + state03_we = 1; + + ADDR_DIGEST4: + state04_we = 1; + + ADDR_DIGEST5: + state05_we = 1; + + ADDR_DIGEST6: + state06_we = 1; + + ADDR_DIGEST7: + state07_we = 1; + + ADDR_DIGEST8: + state08_we = 1; + + ADDR_DIGEST9: + state09_we = 1; + + ADDR_DIGEST10: + state10_we = 1; + + ADDR_DIGEST11: + state11_we = 1; + + ADDR_DIGEST12: + state12_we = 1; + + ADDR_DIGEST13: + state13_we = 1; + + ADDR_DIGEST14: + state14_we = 1; + + ADDR_DIGEST15: + state15_we = 1; + default: begin tmp_error = 1; -- cgit v1.2.3