From 6f28e4f30356e8e07941b9fe87a0debc26f89f8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 11 Sep 2014 17:42:34 +0200 Subject: Changed to asynch reset. --- src/rtl/sha512.v | 4 ++-- src/rtl/sha512_core.v | 4 ++-- src/rtl/sha512_w_mem.v | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v index e3608e7..c9c388b 100644 --- a/src/rtl/sha512.v +++ b/src/rtl/sha512.v @@ -278,10 +278,10 @@ module sha512( // reg_update // // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous + // All registers are positive edge triggered with asynchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v index c3a2de6..73bbcee 100644 --- a/src/rtl/sha512_core.v +++ b/src/rtl/sha512_core.v @@ -198,10 +198,10 @@ module sha512_core( //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous + // All registers are positive edge triggered with asynchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v index 57e6d68..47113b9 100644 --- a/src/rtl/sha512_w_mem.v +++ b/src/rtl/sha512_w_mem.v @@ -105,10 +105,10 @@ module sha512_w_mem( //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. - // All registers are positive edge triggered with synchronous + // All registers are positive edge triggered with asynchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update if (!reset_n) begin -- cgit v1.2.3