From 4ebdf3e80842e38906d85badbbaf25435aa85677 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 4 Dec 2018 13:20:17 +0100 Subject: Added reg on output from w_mem to split long path. Adjusted when w_next is set to update w_mem to account for delay cycle. --- src/rtl/sha512_core.v | 15 +++++++-------- src/rtl/sha512_w_mem.v | 32 +++++++++++++------------------- 2 files changed, 20 insertions(+), 27 deletions(-) diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v index 407f84c..6f6f821 100644 --- a/src/rtl/sha512_core.v +++ b/src/rtl/sha512_core.v @@ -79,12 +79,11 @@ module sha512_core( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter SHA512_ROUNDS = 79; - - parameter CTRL_IDLE = 0; - parameter CTRL_T1_T2 = 1; - parameter CTRL_ROUNDS = 2; - parameter CTRL_DONE = 3; + localparam SHA512_ROUNDS = 79; + localparam CTRL_IDLE = 0; + localparam CTRL_T1_T2 = 1; + localparam CTRL_ROUNDS = 2; + localparam CTRL_DONE = 3; //---------------------------------------------------------------- @@ -634,7 +633,8 @@ module sha512_core( CTRL_T1_T2: begin - t1_t2_we = 1; + t1_t2_we = 1; + w_next = 1; sha512_ctrl_new = CTRL_ROUNDS; sha512_ctrl_we = 1; end @@ -642,7 +642,6 @@ module sha512_core( CTRL_ROUNDS: begin - w_next = 1; state_update = 1; round_ctr_inc = 1; diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v index e0a6775..4aadb50 100644 --- a/src/rtl/sha512_w_mem.v +++ b/src/rtl/sha512_w_mem.v @@ -83,12 +83,14 @@ module sha512_w_mem( reg [6 : 0] w_ctr_new; reg w_ctr_we; + reg [63 : 0] w_reg; + reg [63 : 0] w_new; + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- reg [63 : 0] w_tmp; - reg [63 : 0] w_new; //---------------------------------------------------------------- @@ -105,28 +107,20 @@ module sha512_w_mem( //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin : reg_update + integer i; + if (!reset_n) begin - w_mem[00] <= 64'h0; - w_mem[01] <= 64'h0; - w_mem[02] <= 64'h0; - w_mem[03] <= 64'h0; - w_mem[04] <= 64'h0; - w_mem[05] <= 64'h0; - w_mem[06] <= 64'h0; - w_mem[07] <= 64'h0; - w_mem[08] <= 64'h0; - w_mem[09] <= 64'h0; - w_mem[10] <= 64'h0; - w_mem[11] <= 64'h0; - w_mem[12] <= 64'h0; - w_mem[13] <= 64'h0; - w_mem[14] <= 64'h0; - w_mem[15] <= 64'h0; - w_ctr_reg <= 7'h00; + for (i = 0 ; i < 16 ; i = i + 1) + w_mem[i] <= 64'h0; + + w_ctr_reg <= 7'h0; + w_reg <= 64'h0; end else begin + w_reg <= w_new; + if (w_mem_we) begin w_mem[00] <= w_mem00_new; @@ -169,7 +163,7 @@ module sha512_w_mem( end else begin - w_tmp = w_new; + w_tmp = w_reg; end end // select_w -- cgit v1.2.3