From 00f002c478e718d8bc6a71d148816820a8e65fc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 3 Apr 2018 11:59:25 +0200 Subject: Non functional cleanups: (1) Changed name of round counter to show what is used for. (2) Fixed timescale and empty parentheses of tasks in testbenches. (3) Fixed targets in Makefile to build if needed. --- src/rtl/sha512_core.v | 64 +++++++++++++++++++++++++------------------------ src/tb/tb_sha512.v | 19 ++++++--------- src/tb/tb_sha512_core.v | 21 +++++++--------- toolruns/Makefile | 7 +++--- 4 files changed, 51 insertions(+), 60 deletions(-) diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v index 9454f40..01f124d 100644 --- a/src/rtl/sha512_core.v +++ b/src/rtl/sha512_core.v @@ -126,11 +126,11 @@ module sha512_core( reg [63 : 0] H7_new; reg H_we; - reg [6 : 0] t_ctr_reg; - reg [6 : 0] t_ctr_new; - reg t_ctr_we; - reg t_ctr_inc; - reg t_ctr_rst; + reg [6 : 0] round_ctr_reg; + reg [6 : 0] round_ctr_new; + reg round_ctr_we; + reg round_ctr_inc; + reg round_ctr_rst; reg [31 : 0] work_factor_ctr_reg; reg [31 : 0] work_factor_ctr_new; @@ -147,6 +147,7 @@ module sha512_core( reg [1 : 0] sha512_ctrl_new; reg sha512_ctrl_we; + reg [63 : 0] t1_reg; //---------------------------------------------------------------- // Wires. @@ -184,7 +185,7 @@ module sha512_core( // Module instantiantions. //---------------------------------------------------------------- sha512_k_constants k_constants_inst( - .addr(t_ctr_reg), + .addr(round_ctr_reg), .K(k_data) ); @@ -254,11 +255,14 @@ module sha512_core( H7_reg <= 64'h0000000000000000; work_factor_ctr_reg <= 32'h00000000; digest_valid_reg <= 0; - t_ctr_reg <= 7'h00; + round_ctr_reg <= 7'h0; sha512_ctrl_reg <= CTRL_IDLE; + t1_reg <= 64'h0; end else begin + t1_reg <= t1; + if (a_h_we) begin a_reg <= a_new; @@ -331,9 +335,9 @@ module sha512_core( if (state15_we) H7_reg <= {H7_reg[63 : 32], state_wr_data}; - if (t_ctr_we) + if (round_ctr_we) begin - t_ctr_reg <= t_ctr_new; + round_ctr_reg <= round_ctr_new; end if (work_factor_ctr_we) @@ -501,28 +505,28 @@ module sha512_core( //---------------------------------------------------------------- - // t_ctr + // round_ctr // // Update logic for the round counter, a monotonically // increasing counter with reset. //---------------------------------------------------------------- always @* - begin : t_ctr - t_ctr_new = 7'h00; - t_ctr_we = 0; + begin : round_ctr + round_ctr_new = 7'h0; + round_ctr_we = 0; - if (t_ctr_rst) + if (round_ctr_rst) begin - t_ctr_new = 7'h00; - t_ctr_we = 1; + round_ctr_new = 7'h00; + round_ctr_we = 1; end - if (t_ctr_inc) + if (round_ctr_inc) begin - t_ctr_new = t_ctr_reg + 1'b1; - t_ctr_we = 1; + round_ctr_new = round_ctr_reg + 1'b1; + round_ctr_we = 1; end - end // t_ctr + end // round_ctr //---------------------------------------------------------------- @@ -567,7 +571,6 @@ module sha512_core( state_init = 0; state_update = 0; - t1_we = 0; first_block = 0; ready_flag = 0; @@ -575,8 +578,8 @@ module sha512_core( w_init = 0; w_next = 0; - t_ctr_inc = 0; - t_ctr_rst = 0; + round_ctr_inc = 0; + round_ctr_rst = 0; digest_valid_new = 0; digest_valid_we = 0; @@ -600,7 +603,7 @@ module sha512_core( w_init = 1; state_init = 1; first_block = 1; - t_ctr_rst = 1; + round_ctr_rst = 1; digest_valid_new = 0; digest_valid_we = 1; sha512_ctrl_new = CTRL_ROUNDS1; @@ -612,7 +615,7 @@ module sha512_core( work_factor_ctr_rst = 1; w_init = 1; state_init = 1; - t_ctr_rst = 1; + round_ctr_rst = 1; digest_valid_new = 0; digest_valid_we = 1; sha512_ctrl_new = CTRL_ROUNDS1; @@ -623,7 +626,6 @@ module sha512_core( CTRL_ROUNDS1: begin - t1_we = 1; sha512_ctrl_new = CTRL_ROUNDS2; sha512_ctrl_we = 1; end @@ -631,11 +633,11 @@ module sha512_core( CTRL_ROUNDS2: begin - w_next = 1; - state_update = 1; - t_ctr_inc = 1; + w_next = 1; + state_update = 1; + round_ctr_inc = 1; - if (t_ctr_reg == SHA512_ROUNDS) + if (round_ctr_reg == SHA512_ROUNDS) begin work_factor_ctr_inc = 1; sha512_ctrl_new = CTRL_DONE; @@ -651,7 +653,7 @@ module sha512_core( begin w_init = 1; state_init = 1; - t_ctr_rst = 1; + round_ctr_rst = 1; sha512_ctrl_new = CTRL_ROUNDS1; sha512_ctrl_we = 1; end diff --git a/src/tb/tb_sha512.v b/src/tb/tb_sha512.v index a0dcb4c..8bc0068 100644 --- a/src/tb/tb_sha512.v +++ b/src/tb/tb_sha512.v @@ -37,11 +37,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - //------------------------------------------------------------------ // Test module. @@ -202,7 +197,7 @@ module tb_sha512(); // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("State of DUT"); $display("------------"); @@ -257,7 +252,7 @@ module tb_sha512(); // // Toggles reset to force the DUT into a well defined state. //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -275,7 +270,7 @@ module tb_sha512(); // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 32'h00000000; error_ctr = 32'h00000000; @@ -296,7 +291,7 @@ module tb_sha512(); // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_result(); + task display_test_result; begin if (error_ctr == 0) begin @@ -321,7 +316,7 @@ module tb_sha512(); // when the dut is actively processing and will in fact at some // point set the flag. //---------------------------------------------------------------- - task wait_ready(); + task wait_ready; begin read_data = 0; @@ -431,7 +426,7 @@ module tb_sha512(); // // Read the name and version from the DUT. //---------------------------------------------------------------- - task check_name_version(); + task check_name_version; reg [31 : 0] name0; reg [31 : 0] name1; reg [31 : 0] version; @@ -459,7 +454,7 @@ module tb_sha512(); // Read the digest in the dut. The resulting digest will be // available in the global variable digest_data. //---------------------------------------------------------------- - task read_digest(); + task read_digest; begin read_word(ADDR_DIGEST0); digest_data[511 : 480] = read_data; diff --git a/src/tb/tb_sha512_core.v b/src/tb/tb_sha512_core.v index b8523a0..8aeaa33 100644 --- a/src/tb/tb_sha512_core.v +++ b/src/tb/tb_sha512_core.v @@ -37,11 +37,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/10ps - //------------------------------------------------------------------ // Test module. @@ -134,7 +129,7 @@ module tb_sha512_core(); // // Dump the state of the dut. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("State of DUT"); $display("------------"); @@ -160,8 +155,8 @@ module tb_sha512_core(); dut.state_init, dut.state_update); $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x", dut.first_block, dut.ready_flag, dut.w_init); - $display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x", - dut.t_ctr_inc, dut.t_ctr_rst, dut.t_ctr_reg); + $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x", + dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg); $display(""); $display("State registers:"); @@ -189,7 +184,7 @@ module tb_sha512_core(); // // Dump the state of the dut wmem. //---------------------------------------------------------------- - task dump_dut_wmem(); + task dump_dut_wmem; begin $display("State of DUT WMEM"); $display("-----------------"); @@ -215,7 +210,7 @@ module tb_sha512_core(); // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -231,7 +226,7 @@ module tb_sha512_core(); // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 0; error_ctr = 0; @@ -254,7 +249,7 @@ module tb_sha512_core(); // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_result(); + task display_test_result; begin if (error_ctr == 0) begin @@ -277,7 +272,7 @@ module tb_sha512_core(); // when the dut is actively processing and will in fact at some // point set the flag. //---------------------------------------------------------------- - task wait_ready(); + task wait_ready; begin while (!tb_ready) begin diff --git a/toolruns/Makefile b/toolruns/Makefile index f58bb38..39e272d 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -50,14 +50,14 @@ LINT=verilator LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME -all: top core +all: top.sim core.sim -top: $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC) +top.sim: $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC) $(CC) $(CC_FLAGS) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) $(CORE_SRC) -core: $(CORE_TB_SRC) $(CORE_SRC) +core.sim: $(CORE_TB_SRC) $(CORE_SRC) $(CC) $(CC_FLAGS) -o core.sim $(CORE_SRC) $(CORE_TB_SRC) @@ -76,7 +76,6 @@ lint: $(TOP_SRC) $(CORE_SRC) clean: rm -f top.sim rm -f core.sim - rm -f wmem.sim help: -- cgit v1.2.3