core/hash/sha512 - Verilog implementation of the SHA-512 hash function

Age	Commit message (Expand)	Author
2018-10-19	Cleaned up the code as part of fixing issues found during the audit.	Joachim Strömbergson
2018-04-23	Correcting name for t1 and t2 update vectors. Cleaned up constants.	Joachim Strömbergson
2018-04-06	Updated state display. Added cycle count display.	Joachim Strömbergson
2018-04-06	Added registers for t1 and t2. Updated tb to look at update vectors.	Joachim Strömbergson
2018-04-06	Minor cleanup of mask definition to make it easier to understand.	Joachim Strömbergson
2018-04-03	Changed constant declaraiton to use hex radix. Removed now redundant flag sig...	Joachim Strömbergson
2018-04-03	Connected all dangling dut ports in the core testbench. Fixed RTL code that c...	Joachim Strömbergson
2018-04-03	Non functional cleanups: (1) Changed name of round counter to show what is us...	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-07-18	Completed test case for state restore. The state restore functionality works....	Joachim Strömbergson
2015-07-18	Adding initial version of test case for state restore functionality.	Joachim Strömbergson
2014-11-20	Adding work factor processing functionality.	Joachim Strömbergson
2014-11-06	Fixes of nits in #8 found with the verilator linter.	Joachim Strömbergson
2014-04-05	Adding core and top level testbenches for sha512.	Joachim Strömbergson