core/hash/sha512 - Verilog implementation of the SHA-512 hash function

Age	Commit message (Collapse)	Author
2018-04-03	Connected all dangling dut ports in the core testbench. Fixed RTL code that ↵	Joachim Strömbergson
	caused event loop in Icarus. Does not change functionality.
2018-04-03	Non functional cleanups: (1) Changed name of round counter to show what is ↵	Joachim Strömbergson
	used for. (2) Fixed timescale and empty parentheses of tasks in testbenches. (3) Fixed targets in Makefile to build if needed.
2018-04-03	Added second round state to allow for one cycle propagation of t1 in a ↵	Joachim Strömbergson
	future register.
2015-12-13	whack copyrights	Paul Selkirk

2015-07-18	Adding logic to write state restore data to the state registers.	Joachim Strömbergson

2015-07-18	Added API logic to set write signals for the state.	Joachim Strömbergson

2015-07-18	Adding ports in the core to do state restore. Added wires in the top to ↵	Joachim Strömbergson
	connect the state restore ports.
2015-03-31	Revert streamlined wrapper, and don't delay register reads.	Paul Selkirk

2015-03-17	Rearrange cores.	Paul Selkirk

2014-11-20	Adding work factor processing functionality.	Joachim Strömbergson

2014-11-06	Fixes of nits in #8 found with the verilator linter.	Joachim Strömbergson

2014-09-11	Changed to asynch reset.	Joachim Strömbergson

2014-04-05	Adding source RTL files for the sha512 core.	Joachim Strömbergson