From f762c8d4e4ae3335c3340ac24ecc9c58606f7163 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Sun, 6 Jun 2021 22:04:55 -0400 Subject: The SHA-3 algorithm really wants everything to be little-endian, which is at odds with everything else in our system (including the register interface to sha3_wrapper). Rather than trying to rewrite Bernd's beautiful code, I'll isolate it in its own little-endian universe by byte-swapping all reads and writes. --- src/rtl/sha3.v | 46 +++++++++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 15 deletions(-) (limited to 'src/rtl') diff --git a/src/rtl/sha3.v b/src/rtl/sha3.v index ee29ba6..869d142 100644 --- a/src/rtl/sha3.v +++ b/src/rtl/sha3.v @@ -44,14 +44,30 @@ `define SHA3_NUM_ROUNDS 5'd24 module sha3( input wire clk, - input wire nreset, - input wire w, - input wire [ 8:2] addr, - input wire [32-1:0] din, - output reg [32-1:0] dout, - input wire init, - input wire next, - output wire ready); + input wire nreset, + input wire w, + input wire [ 8:2] addr, + input wire [32-1:0] din, + output wire [32-1:0] dout, + input wire init, + input wire next, + output wire ready); + + + /* + * The SHA-3 algorithm really wants everything to be little-endian, + * which is at odds with everything else in our system (including the + * register interface to sha3_wrapper). Rather than trying to rewrite + * Bernd's beautiful code, I'll isolate it in its own little-endian + * universe by byte-swapping all reads and writes. + */ + + reg [31:0] dout_swap; + assign dout = {dout_swap[7:0], dout_swap[15:8], dout_swap[23:16], dout_swap[31:24]}; + + wire [31:0] din_swap; + assign din_swap = {din[7:0], din[15:8], din[23:16], din[31:24]}; + integer i, j; @@ -100,9 +116,9 @@ module sha3( input wire clk, always @* // - dout = addr[8] ? - (~addr[2] ? st [addr[7:3]][31:0] : st [addr[7:3]][63:32]) : - (~addr[2] ? blk[addr[7:3]][31:0] : blk[addr[7:3]][63:32]) ; + dout_swap = addr[8] ? + (~addr[2] ? st [addr[7:3]][31:0] : st [addr[7:3]][63:32]) : + (~addr[2] ? blk[addr[7:3]][31:0] : blk[addr[7:3]][63:32]) ; always @* begin @@ -188,12 +204,12 @@ module sha3( input wire clk, end - if (w && !addr[8]) // only the first half of memory is writeable + if (w) // case (addr[2]) - 1: blk[addr[7:3]][63:32] <= din; - 0: blk[addr[7:3]][31: 0] <= din; - endcase // case (addr[2]) + 1: blk[addr[7:3]][63:32] <= din_swap; + 0: blk[addr[7:3]][31: 0] <= din_swap; + endcase end -- cgit v1.2.3